Dma Control Register; Pci Controller Interrupt Enable Register - Intel IXP45X Developer's Manual

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PCI Controller—Intel IXP45X and Intel
10.5.3.10

PCI Controller Interrupt Enable Register

Register Name:
Block
0xC00000
Base Address:
Interrupt enables for the interrupt status bits in the pci_isr register.
Register Description:
Set to a 1 to enable the particular interrupt.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
31:8 reserved reserved – read as 0
7 PDB PCI Doorbell interrupt enable.
6 ADB AHB Doorbell interrupt enable.
5 PADC PCI-to-AHB DMA Complete interrupt enable.
4 APDC AHB-to-PCI DMA Complete interrupt enable.
3 AHBE AHB Error indication interrupt enable.
2 PPE PCI Parity Error interrupt enable.
1 PFE PCI Fatal Error interrupt enable.
0 PSE PCI System Error interrupt enable.
10.5.3.11

DMA Control Register

Register Name:
Block
0xC00000
Base Address:
Control and status for the DMA Controller channels.
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
(Reserved)
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
Offset Address
(Reserved)
Description
Offset Address
®
Intel IXP45X and Intel
pci_inten
0x24
Reset Value
8 7
pci_inten
pci_dmactrl
0x28
Reset Value
8 7
(Reserved) APDE1
®
IXP46X Product Line of Network Processors
0x00000000
Access: (See below.)
6 5 4 3 2 1 0
Reset PCI AHB
Value Access Access
0x0000
RO RO
00
0 RO RW
0 RO RW
0 RO RW
0 RO RW
0 RO RW
0 RO RW
0 RO RW
0 RO RW
0x00000000
Access: (See below.)
6 5 4 3 2 1 0
APDE0 (Rsv'd)
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