Udc Interrupt Control Register 1; Interrupt Mask Endpoint X (Imx), Where X Is 8 Through 15 - Intel IXP45X Developer's Manual

USB 1.1 Device Controller—Intel
Processors
Bits
2
1
0
8.5.19

UDC Interrupt Control Register 1

The UICR1 contains eight control bits to enable/disable interrupt service requests from
Endpoints 8 through 15. The UICR1 bits are reset to 1 so interrupts are not generated
on initial system reset.
8.5.19.1

Interrupt Mask Endpoint x (IMx), where x is 8 through 15

The UICR1[IMx] bit is used to mask or enable the corresponding endpoint interrupt
request, USIR1[IRx]. When the mask bit is set, the interrupt is masked and the
corresponding bit in the USIR1 register is not allowed to be set.
When the mask bit is cleared and an interruptible condition occurs in the endpoint, the
appropriate interrupt bit is set. Programming the mask bit to a 1 does not affect the
current state of the interrupt bit. It only blocks future 0-to-1 transitions of the interrupt
bit.
Register Name:
0 x C800B054
Hex Offset Address:
Register
Universal Serial Bus Device Controller Interrupt Control Register 1
Description:
Access: Read/Write
31
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network
Register
Name
Interrupt Mask for Endpoint 2.
IM2 0 = Receive interrupt enabled.
1 = Receive interrupt disabled.
Interrupt Mask for Endpoint 1.
IM1 0 = Transmit interrupt enabled.
1 = Transmit interrupt disabled.
Interrupt mask for endpoint 0.
IM0 0 = Endpoint zero interrupt enabled.
1 = Endpoint zero interrupt disabled.
Bits
(Reserved)
Resets (Above)
Intel
UICR0
(Sheet 2 of 2)
Description
UICR1
0x000000FF
Reset Hex Value:
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
(UICR1)
8 7 6 5 4 3 2 1
1 1 1 1 1 1 1
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