Udc Endpoint 7 Control/Status Register - Intel IXP45X Developer's Manual

USB 1.1 Device Controller—Intel
Processors
Bits
3
2
1
0
8.5.9

UDC Endpoint 7 Control/Status Register

The UDC Endpoint 7 Control/Status Register contains seven bits that are used to
operate Endpoint 7, a Bulk OUT endpoint.
8.5.9.1 Receive FIFO Service (RFS)
The receive FIFO service bit is set if the receive FIFO has one complete data packet in it
and the packet has been error checked by the UDC. A complete packet may be
64 bytes, a short packet, or a zero packet.
This bit is not cleared until all data has been read from both buffers.
8.5.9.2 Receive Packet Complete (RPC)
The receive packet complete bit is set by the UDC when an OUT packet is received.
When this bit is set, the IR7 bit in the appropriate UDC status/interrupt register is set
— if receive interrupts are enabled.
This bit can be used to validate the other status/error bits in the Endpoint 7 Control/
Status Register. The UDCCS7 [RPC] bit is cleared by writing a 1 to it. The UDC issues
NAK handshakes to all OUT tokens while this bit is set and both buffers have unread
data.
8.5.9.3 Bit 2 Reserved
Bit 2 is reserved for future use.
8.5.9.4 Bit 3 Reserved
Bit 3 is reserved for future use.
8.5.9.5 Sent Stall (SST)
The sent stall bit is set by the UDC in response to FST successfully forcing a user-
induced STALL on the USB bus. This bit is not set if the UDC detects a protocol violation
from the host PC when a STALL handshake is returned automatically. In either event,
the Intel XScale processor does not intervene and the UDC clears the STALL status
when the host sends a CLEAR_FEATURE command.
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network
Register
Name
Transmit FIFO underrun (read/write 1 to clear).
TUR
1 = Transmit FIFO experienced an underrun.
Flush Tx FIFO (always read 0/ write a 1 to set).
FTF
1 = Flush Contents of TX FIFO.
Transmit packet complete (read/write 1 to clear).
TPC 0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
Transmit FIFO service (read-only).
TFS 0 = Transmit FIFO has no room for new data.
1 = Transmit FIFO has room for at least 1 complete data packet.
Intel
UDCCS6
(Sheet 2 of 2)
Description
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
(UDCCS7)
Developer's Manual
309