Previous Master/Slave Register - Intel IXP45X Developer's Manual

Performance Monitoring Unit (PMU)—Intel
Processors
Register Name:
Physical Address:
Register Description:
Access: Read
(Reserved)
Register
Bits Name
31:2
(Reserved) Always zero.
7
26:0 PECx This is a 27-bit, read-only counter register.
16.6.5

Previous Master/Slave Register

This register encodes the device which previously accessed or was being accessed on
the monitored buses.
This register is reset, but the reset value is quickly overwritten with the bus activity, so
the reset value has little practical meaning. This value reflects the last recorded
activity. To build up a histogram of master/slave pairs this register would be read
periodically. However there is no way to know that an unchanging value means that
there was no bus activity.
Register Name:
Physical Address:
Register Description:
Access: Read
(Reserved)
August 2006
Order Number: 306262-004US
®
IXP45X and Intel
0xC800 2020
0xC800 2024
0xC800 2028
0xC800 202C
0xC800 2030
0xC800 2034
0xC800 2038
0xC800 203C
Event Counter
Description
0xC800 2018
Bus activity master.slave
MPI
Intel
®
IXP46X Product Line of Network
PECx
Reset Hex Value:
PECx
PECx
PMSR
Reset Hex Value:
PSS PSN
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
0x00000000
Reset
Access
Value
0x0000000 R
PMSR
0x00000000
PMS PMN
Developer's Manual
797