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Expansion Bus Controller—Intel
Processors
12.5.1
Timing and Control Registers for Chip Select 0
Register Name:
Hex Offset Address:
0XC4000000
Register
Timing and Control Registers
Description:
Access: Read/Write
31 30 29 28 27 26 25
T1
T2
T
Note:
The undefined (X) in the reset value is dependent upon values supplied to the chip on
the Expansion Bus address during the reset sequence. Please refer to
"Configuration Register 0" on page 706
12.5.2
Timing and Control Registers for Chip Select 1
Register Name:
0XC4000004
Hex Offset Address:
Register
Timing and Control Registers
Description:
Access: Read/Write
31 30 29 28 27 26 25
T1
T2
12.5.3
Timing and Control Registers for Chip Select 2
Register Name:
0XC4000008
Hex Offset Address:
Register
Timing and Control Registers
Description:
Access: Read/Write.
31 30 29 28 27 26 25
T1
T2
August 2006
Order Number: 306262-004US
®
®
IXP45X and Intel
IXP46X Product Line of Network
22 21 20 19
T3
T4
T5
22 21 20 19
T3
T4
T5
22 21 20 19
T3
T4
T5
EXP_TIMING_CS0
Reset Hex Value:
0xBFFF3C4x
16 15 14 13
CNFG[4:0]
for additional details.
EXP_TIMING_CS1
Reset Hex Value:
0x00000000
16 15 14 13
CNFG[4:0]
EXP_TIMING_CS2
Reset Hex Value:
0x00000000
16 15 14 13
CNFG[4:0]
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
CS0:
9
8
7
6
5
4
3
2
Section 12.5.9,
CS1:
9
8
7
6
5
4
3
2
CS2:
9
8
7
6
5
4
3
2
Developer's Manual
1
0
1
0
1
0
703
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