Pci Controller Functioning As Bus Target; Pci Controller Door Bell Register; Initiated Pci Burst Memory Write Cycle - Intel IXP45X Developer's Manual

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PCI Controller—Intel IXP45X and Intel
Figure 89.

Initiated PCI Burst Memory Write Cycle

PCI_CLK
INT_REQ_N
INT_GNT_N
PCI_FRAME_N
PCI_AD (31:0)
PCI_IDSEL
PCI_CBE_N
PCI_IRDY_N
PCI_TRDY_N
PCI_DEVSEL_N
10.2.8

PCI Controller Functioning as Bus Target

The IXP45X/IXP46X network processors can be the target of PCI transactions.
Operating as a PCI target, the PCI bus can accept Memory Cycles, I/O Cycles, or
Configuration Cycles. Target transactions can take place independent of the Host/
Option configuration of the IXP45X/IXP46X network processors. Please refer to
Table 189, "PCI Target Interface Supported Commands" on page 498
information on supported commands.
Only Type 0 Configuration Cycles are supported.
Timing diagrams are not shown for the target transactions because they are similar to
initiated transactions. The only differences are the PCI devices that source/sink the
various PCI signals.
For target-read transactions, a retry will be issued upon the receipt of a request to
transfer data. Between the time that the retry occurs and the access to the IXP45X/
IXP46X network processors reoccurs, the PCI Controller retrieves the data from the
previously requested location.
For additional details, see the PCI Local Bus Specification, Rev. 2.2.
10.2.9

PCI Controller Door Bell Register

The PCI Controller has two registers that make up the Door Bell register logic on the
IXP45X/IXP46X network processors. These two registers are the AHB Door Bell
(PCI_AHBDOORBELL) register and the PCI Door Bell Register (PCI_PCIDOORBELL).
An external PCI device writes the AHB Door Bell (PCI_AHBDOORBELL) register to
generate an interrupt signal to the Intel XScale processor. If the AHB doorbell interrupt
is enabled (PCI_INTEN.ADBEN = 1) in the PCI interrupt registers, any bit set to logic 1
in the AHB Door Bell (PCI_AHBDOORBELL) will force the interrupt signal to occur.
The AHB Door Bell (PCI_AHBDOORBELL) register is set from the PCI bus only by writing
logic 1 to the register.
that are set in the AHB Door Bell (PCI_AHBDOORBELL).
An example of using the AHB Door Bell (PCI_AHBDOORBELL) is as follows:
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
0x00000014 DATA 0
0x7
Writing logic 1 to the set bits from the SOUTH AHB clears bits
®
Intel IXP45X and Intel
DATA 1
0x0
®
IXP46X Product Line of Network Processors
B4292-01
for additional
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