Stop Condition; Serial Clock Line (Scl) Generation; Start And Stop Condition Events - Intel IXP45X Developer's Manual

I2C Bus Interface Unit—Intel
21.4.3.3

STOP Condition

The STOP condition (bits 1:0 of the ICR set to 2'b10) terminates a data transfer. In
master-transmit mode, the STOP bit and the Transfer Byte bit in the ICR must be set to
initiate the last byte transfer (see
must set the Ack/Nack bit, the STOP bit, and the Transfer Byte bit in the ICR to initiate
the last transfer. Software must clear the STOP condition after it is transmitted.
Figure 193. START and STOP Condition Events
START Condition
START
STOP Condition
2
21.5 I C Bus Operation
2
The I C Bus Interface Unit transfers in 1 byte increments. A data transfer on the I
bus always follows the sequence:
1. START
2. 7-bit Slave Address
3. R/W# Bit
4. Acknowledge Pulse
5. 8 Bits of Data
6. Ack/Nack Pulse
7. Repeat of Step 5 and 6 for Required Number of Bytes
8. Repeated START (Repeat Step 1) or STOP
21.5.1

Serial Clock Line (SCL) Generation

2
The I C unit of the IXP45X/IXP46X network processors is required to generate the I
clock output when in master mode (either receive or transmit). SCL clock generation is
accomplished through the use of the ICCR value, which is programmed at initialization.
Equation 11
Equation 11. SCL Transition Period
SCL Transition Period = (ICCR Decimal Value + 1) * (processor-supplied clock period) *
(167 - (Fast Mode Enable *125))
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Data Byte
Target Slave Address
Data Byte R/W#
shows how the ICCR value is used to determine the SCL transition period:
Figure 192). In master-receive mode, the processor
Ack/
Nack
Ack/
R/W#
Nack
Ack/
STOP
Nack
B4258-01
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
2
C
2
C
Developer's Manual
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