Udc Endpoint 9 Control/Status Register - Intel IXP45X Developer's Manual

USB 1.1 Device Controller—Intel
Processors
Bits
31:8
7
6
5
4
3
2
1
0
8.5.11

UDC Endpoint 9 Control/Status Register

The UDC Endpoint 9 Control/Status Register contains six bits that are used to operate
Endpoint 9, an isochronous OUT endpoint.
8.5.11.1 Receive FIFO Service (RFS)
The receive FIFO service bit is set if the receive FIFO has one complete data packet in it
and the packet has been error checked by the UDC. A complete packet may be
256 bytes, a short packet, or a zero packet. UDCCS9[RFS] is not cleared until all data is
read from both buffers.
8.5.11.2 Receive Packet Complete (RPC)
The receive packet complete bit gets set by the UDC when an OUT packet is received.
When this bit is set, the IR9 bit in the appropriate UDC status/interrupt register is set if
receive interrupts are enabled.
This bit can be used to validate the other status/error bits in the Endpoint 9 Control/
Status Register. The UDCCS9[RPC] bit is cleared by writing a 1 to it.
8.5.11.3 Receive Overflow (ROF)
The receive overflow bit generates an interrupt on IR9 in the appropriate UDC status/
interrupt register to alert the software that Isochronous data packets are being
dropped because neither FIFO buffer has room for them. This bit is cleared by writing a
1 to it.
8.5.11.4 Bit 3 Reserved
Bit 3 is reserved for future use.
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network
Register
Name
Reserved for future use.
Transmit short packet (read/write 1 to set).
TSP
1 = Short packet ready for transmission.
(Reserved). Always reads 0.
(Reserved). Always reads 0.
(Reserved). Always reads 0.
Transmit FIFO underrun (read/write 1 to clear).
TUR
1= Transmit FIFO experienced an underrun.
Flush Tx FIFO (always read 0/ write a 1 to set).
FTF
1 = Flush Contents of TX FIFO.
Transmit packet complete (read/write 1 to clear).
TPC 0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
Transmit FIFO service (read-only).
TFS 0 = Transmit FIFO has no room for new data.
1 = Transmit FIFO has room for at least 1 complete data packet.
Intel
UDCCS8
Description
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
(UDCCS9)
Developer's Manual
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