Transmit Deferral Parameter; Receive Deferral Parameter; Transmit Two Part Deferral Parameters 1 - Intel IXP45X Developer's Manual

®
Ethernet MACs—Intel IXP45X and Intel
6.2.15

Transmit Deferral Parameter

Register Name:
0xC8009050
Hex Offset Address:
Register
Transmit/Receive Deferral Parameters
Description:
Access: Read/Write.
31
Bits
31:8
7:0
6.2.16

Receive Deferral Parameter

Register Name:
0xC8009054
Hex Offset Address:
Register
Transmit/Receive Deferral Parameters
Description:
Access: Read/Write.
31
Bits
31:8
7:0
6.2.17

Transmit Two Part Deferral Parameters 1

Register Name:
0xC8009060
Hex Offset Address:
Register
Transmit Two Part Deferral Parameters Register.
Description:
Access: Read/Write.
31
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
(Reserved)
Register
Name
(Reserved)
Single Number of transmit clock cycles (tx_clk) in the transmit deferral period minus
deferral three, when single deferral is used for transmission (Transmit Control[15] = 0).
(Reserved)
Register
Name
(Reserved)
Number of receive clock cycles (rx_clk) in the receive deferral period minus
Receive
three, when checking the Inter Frame Gap for packets received (Receive Control
Deferral
2[0] = 0).
(Reserved)
Intel
txdefpars
0x00000000
Reset Hex Value:
txdefpars
Description
rxdefpars
0x00000000
Reset Hex Value:
rxdefpars
Description
tx2partdefpars1
0x00000000
Reset Hex Value:
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
8 7
Transmit Deferral
8 7
Receive Deferral
8 7
First Deferral Period
Developer's Manual
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