Intel IXP45X Developer's Manual page 94

Intel
Example 11. Creating Data RAM
; R1 contains the virtual address of a region of memory to configure as data RAM,
; which is aligned on a 32-byte boundary.
; MMU is configured so that the memory region is cacheable.
; R0 is the number of 32-byte lines to designate as data RAM. In this example 16
; lines of the data cache are re-configured as data RAM.
; The inner loop is used to initialize the newly allocated lines
; MMU and data cache are enabled prior to this code.
MACRO ALLOCATE Rx
MCR P15, 0, Rx, C7, C2, 5
ENDM
MACRO DRAIN
MCR P15, 0, R0, C7, C10, 4
ENDM
DRAIN
MOV R4, #0x0
MOV R5, #0x0
MOV R2, #0x1
MCR P15,0,R2,C9,C2,0
CPWAIT
MOV R0, #16
LOOP1:
ALLOCATE R1
; initialize 32 bytes of newly allocated line
DRAIN
STRD R4, [R1],#8
STRD R4, [R1],#8 ;
STRD R4, [R1],#8
STRD R4, [R1],#8
SUBS R0, R0, #1
BNE LOOP1
; Turn off data cache locking
DRAIN
MOV R2, #0x0
MCR P15,0,R2,C9,C2,0; Take the data cache out of lock mode.
CPWAIT
Tags can be locked into the data cache by enabling the data cache lock mode bit
located in coprocessor 15, register 9. (See
page 105
cache will be locked down.
Note that the PLD instruction will not affect the cache contents if it encounters an error
while executing. For this reason, system software should ensure the memory address
used in the PLD is correct. If this cannot be ascertained, replace the PLD with a LDR
instruction that targets a scratch register.
Lines are locked into a set starting at way0 and may progress up to way 27; which set
a line gets locked into depends on the set index of the virtual address of the request.
Figure 7, "Locked Line Effect on Round-Robin Replacement" on page 82
of where lines of code may be locked into the cache along with how the round-robin
pointer is affected.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
94
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
; drain pending loads and stores
; Put the data cache in lock mode
; Allocate and lock a tag into the data cache at
; address [R1].
;
;
;
; Decrement loop count
; Finish all pending operations
for the exact command.) Once enabled, any new lines allocated into the data
Table 22, "Cache Lock-Down Functions" on
Order Number: 306262-004US
®
Processor
is an example
August 2006