Ddri Sdram Address Translation For 128/512 Mbit (X16/X8), 1 Gbitx8; And 256 Mbitx8 Devices; Ddri Sdram Address Translation For 256 Mbitx16 Devices; Mtctr Register Setup - Intel IXP45X Developer's Manual

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Memory Controller—Intel
• Perform DDRI initialization sequence using
SDIR
• Refresh Frequency Register RFR
133MHz
Note: All other registers can use their default register values for operation.
11.2.2.3

MTCTR Register Setup

In order to insure equal bandwidth between the MPI port and the two AHB ports, the
MPTCR register must be programmed to 0x00000011H, other wise the default value
will accept 12 MPI transactions to every one AHB transaction thereby starving the AHB
ports of the memory controller.
11.2.2.4

DDRI SDRAM Addressing

Table 208,
the DDRI_MA[13:0] lines for 128/256/512 Mbit, 1-Gbit DDRI SDRAM devices.
Table 208.

DDRI SDRAM Address Translation for 128/512 Mbit (x16/x8), 1 Gbitx8,

and 256 Mbitx8 Devices

DDRI_MA
13 12
[13:0]
Row
Column
- -
Notes:
1. A10 is used for precharge variations on the read or write command. See
2. For the Leaf Selects, see
Table 209.

DDRI SDRAM Address Translation for 256 Mbitx16 Devices

DDRI_MA
13 12
[13:0]
Row
Column
- -
Notes:
1. A10 is used for precharge variations on the read or write command. See
2. For the Leaf Selects, see
3. 256 Mbitx16 addressing requires that ADDR[24] be presented as bit 12 of the row address instead of ADDR[25] as in
Table 208.
August 2006
Order Number: 306262-004US
®
IXP45X and Intel IXP46X Product Line of Network Processors
register.
Table 209, and Table 210
11 10 9 8
1
V
Table 203.
11 10 9 8
1
V
Table 203.
DDRI SDRAM Initialization Register
- Program per JEDEC Spec using MCU clock of
illustrate how the internal address is mapped to
7 6 5
Table 211
7 6 5
Table 211
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
4 3 2 1
for more details.
4 3 2 1
for more details.
Developer's Manual
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