Intel IXP45X Developer's Manual page 790

Intel
• Split Transfer Latency — Represents the elapsed time between the Requester
receiving a Split Response and the Split claimer transferring the first DWORD of
Data Read.
• Bus Ownership Time — Represents the elapsed time during which an initiator is
in control of the bus.
• Initiator Bus Data Transfer Time — Represents the elapsed time during which
an initiator transfers data.
• Split Data Transfer Time — Represents the elapsed time during which a Split
claimer transfers data (Data Read) to a requester during a split transfer
transaction. Please note that this metric is associated with the requester and not
the split claimer.
Table 255
to the entry in
Table 255. Duration Events (Sheet 1 of 2)
Observe
d
Interface
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
790
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Performance Monitoring
lists the various duration events that are monitored. The Name corresponds
Table 260.
Monitored Event
Number of clocks the AHB bus is doing
Data Writes.
Name: "AHBx Write"
Number of clocks the AHB bus is doing
Data Reads.
Name: "AHBx Read"
Number of clocks the AHB bus is Idle.
Name: "AHBx Idle"
Bus ownership for the AHB Masters.
Name: xAHB[N] Grant Duration"
Bus ownership metrics for the AHB
Masters.
Name: "xAHB[N] Own Duration"
Initiator data transfer time for Writes on
the AHB Masters.
Name: "xAHB[N] WriteDuration"
Initiator data transfer time for Reads on
the AHB Masters.
Name: "xAHB[N] Read Duration"
Description
Increments the counter on every AHB Bus Write data
cycle. This enables calculation of data utilization of the
Write data bus.
Condition:
HWrite = 1 &
HReady = 1 &
HTRANS = (seq OR NonSeq))
Increments the counter on every AHB Bus Read data
cycle. This enables calculation of data utilization of the
Read data bus.
Condition:
HWrite = 0 &
HReady = 1 &
HTRANS = seq or NonSeq
Increments the counter every AHB Bus idle cycle. An
idle cycle occurs when there is no activity on the bus
due to data being transferred and the bus is not in an
overhead cycle. An overhead cycle is a cycle when an
initiator owns the bus, however the initiator is unable
to send data or the target is unable to receive data -
hence no data is transferred.
Condition:
All Grant signals de-asserted
Counts the number of clocks spent by a master
granted the AHB bus.
Counts the duration for which the master is the
initiator on the AHB bus. The counter increments on
every clock cycle during which the master is the bus
initiator.
Increments counter every AHB bus write data cycle
where the master is the initiator.
Increments counter every AHB bus read data cycle
where the master is the initiator.
Order Number: 306262-004US
Unit (PMU)
August 2006