Data Format Of First Byte In Master Transaction - Intel IXP45X Developer's Manual

I2C Bus Interface Unit—Intel
Figure 194. Data Format of First Byte in Master Transaction
Read/Write Transaction
(0) Write
(1) Read
7-Bit
The first byte transmission must be followed by an Ack pulse from the addressed slave.
When the transaction is a write, the I
addressed slave device stays in slave-receive mode. When the transaction is a read,
2
the I C unit transitions to master-receive mode immediately following the Ack and the
addressed slave device transitions to slave-transmit mode. When a Nack is returned,
2
the I C unit aborts the transaction by automatically sending a STOP and setting the ISR
bus error bit.
When the I
and monitors the I
unit reads the first seven bits and compares them to those in the I
Register (ISAR) and the general call address (00H). When the bits match those of the
ISAR register, the I
2
The I C unit either remains in slave-receive mode (R/W# = 0) or transitions to slave-
transmit mode (R/W# = 1). For actions when a general call address is detected, see
"General Call Address" on page
2
21.5.3 I C Acknowledge
2
Every I
always generated by the receiver (master or slave). The transmitter must release the
SDA line for the receiver to transmit the acknowledge pulse (see
In master-transmit mode, when the target slave receiver device cannot generate the
acknowledge pulse, the SDA line remains high. This lack of acknowledge (Nack) causes
2
the I C unit to set the bus error detected bit in the ISR and generate the associated
interrupt (when enabled). The I
automatically.
In master-receive mode, the I
by using the negative acknowledge (Nack). The Ack/Nack bit value driven by the I
bus is controlled by the Ack/Nack bit in the ICR. The bus error detected bit in the ISR is
not set for a master-receive mode Nack (as required by the I
unit automatically transmits the Ack pulse, based on the Ack/Nack ICR bit, after
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IXP45X and Intel IXP46X Product Line of Network Processors
Slave
2
I C
Address
2
C unit is enabled and idle (no bus activity), it stays in slave-receive mode
2
C bus for a START signal. Upon detecting a START pulse, the I
2
C unit reads the eighth bit (R/W# bit) and transmits an Ack pulse.
C byte transfer must be accompanied by an acknowledge pulse, which is
2
7 4
MSB
2
C unit remains in master-transmit mode and the
891.
2
C unit aborts the transaction by generating a STOP
C unit signals the slave-transmitter to stop sending data
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Intel IXP45X and Intel
0
LSB
B4259-01
2
C Slave Address
Figure 195).
2
C bus protocol). The I
IXP46X Product Line of Network Processors
Developer's Manual
2
C
2
C
2
C
883