Scheduling Swp And Swpb Instructions; Scheduling The Mra And Mar Instructions (Mrrc/Mcrr) - Intel IXP45X Developer's Manual

Intel
3.10.5.4

Scheduling SWP and SWPB Instructions

The SWP and SWPB instructions have a five-cycle issue latency. As a result of this
latency, the instruction following the SWP/SWPB instruction would stall for 4 cycles.
SWP and SWPB instructions should, therefore, be used only where absolutely needed.
For example, the following code may be used to swap the contents of two memory
locations:
; Swap the contents of memory locations pointed to by r0 and r1
ldr
swp
str
The code above takes nine cycles to complete. The rewritten code below, takes six
cycles to execute:
; Swap the contents of memory locations pointed to by r0 and r1
ldr
ldr
str
str
3.10.5.5

Scheduling the MRA and MAR Instructions (MRRC/MCRR)

The MRA (MRRC) instruction has an issue latency of one cycle, a result latency of two
or three cycles depending on the destination register value being accessed and a
resource latency of two cycles.
Consider the code sample:
mra
mra
add
The code shown above would incur a one-cycle stall due to the two-cycle resource
latency of an MRA instruction. The code can be rearranged as shown below to prevent
this stall.
mra
add
mra
Similarly, the code shown below would incur a two-cycle penalty due to the three-cycle
result latency for the second destination register.
mra
mov
mov
add
The stalls incurred by the code shown above can be prevented by rearranging the code:
mra
add
mov
mov
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
218
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
r2, [r0]
r2, [r1]
r2, [r1]
r2, [r0]
r3, [r1]
r2, [r1]
r3, [r0]
r6, r7, acc0
r8, r9, acc0
r1, r1, #1
r6, r7, acc0
r1, r1, #1
r8, r9, acc0
r6, r7, acc0
r1, r7
r0, r6
r2, r2, #1
r6, r7, acc0
r2, r2, #1
r0, r6
r1, r7
®
Processor
August 2006
Order Number: 306262-004US