Interrupt Controller; Overview - Intel IXP45X Developer's Manual

Interrupt Controller—Intel
17.0

Interrupt Controller

The Intel XScale
Expanding the interrupt capabilities beyond that of a single source requires an
Interrupt controller external to the Intel XScale processor itself. The APB Interrupt
Controller provides IRQ and FIQ interrupts to the Intel XScale processor. The central
APB Interrupt Controller accepts all interrupts and depending on the software setting,
the interrupts will be passed to the Intel XScale processor.
This version of the interrupt controller extends the number of interrupt sources (as
compared to the controller on the Intel
Network Processor) as well as introducing a new class of "error interrupts." The
modifications to this unit were designed with the following goals in mind:
• Absolute software compatibility is insured by the fact that no current definitions
have been changed, only additional controllability has been added, primarily by
uniformly extending the number of interrupts that can be accommodated.
• A new class of interrupts (typically representing error conditions) have
unconditional highest priority. An example of this would be some kind of fatal
device failure which requires immediate attention.
17.1

Overview

The interrupt controller takes 64 individual interrupts as inputs, refer to
configuration and ordering of all the interrupts. These interrupts originate either in
internal blocks or from GPIO pins. The controller outputs both an IRQ and an FIQ
interrupt to the Intel XScale processor. Any of the 64 input interrupts may be enabled
to produce either the IRQ or FIQ output. The INTR_EN/INTR_EN2 Control Register(s) is
used to enable an interrupt, and the INTR_SEL/INTR_SEL2 Control Register(s) can be
programmed to present an interrupt as an IRQ or an FIQ.
The Intel XScale processor has two methods available to determine which interrupt
within the controller caused the interrupt to assert. The status of the entire 64 bit
interrupt vector may be read from the pair of registers representing INTR_ST/
INTR_ST2. The status of all 64 interrupts enabled as IRQ by INTR_EN/INTR_EN2 may
be read from the pair of registers representing INTR_IRQ_ST/INTR_IRQ_ST2. The
highest priority interrupt pending on the IRQ may be read by INTR_IRQ_ENC_ST. Note
that this register contains an incremented version of the highest priority interrupt, for
example, if the highest priority interrupt number was 3, the register, when read,
returns 4. This incrementing is due to the fact that the number '0' is used to indicate a
spurious or 'no-interrupt' condition. This is also true for the INR_FIQ_ENC_ST register.
Compared to the previous interrupt controller, each of these two vectors is now one bit
wider to enable specification of 64 conditions.
Similarly, INTR_FIQ_ST/INTR_FIQ_ST2 contains all interrupts enabled as FIQ while
INTR_FIQ_ENC_ST holds the "incremented number" of the highest priority FIQ enabled
interrupt pending. Access to all registers is through the APB interface.
It is worth point out that the priority of interrupts only impacts the value in the
INTR_IRQ_ENC_ST and INTR_FIQ_ENC_ST registers. To accelerate the software stack,
these register encode the highest priority as defined by the priority register and the
August 2006
Reference Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
®
Processor supports only a single "IRQ" and "FIQ" interrupt.
®
IXP420 Network Processor and Intel
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
®
IXP425
Table 261 for
Developer's Manual
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