Intel IXP45X Developer's Manual page 143

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Intel XScale Processor—Intel
• HALT mode — Active when the Halt Mode bit is set in the DCSR; prevents only the
mini instruction cache from being invalidated; main instruction cache is invalidated
by reset.
During a cold reset (in which both a processor reset and a JTAG reset occurs) it can be
guaranteed that the instruction cache will be invalidated since the JTAG reset takes the
processor out of any of the modes listed above.
During a warm reset, if a JTAG reset does not occur, the instruction cache is not
invalidated by reset when any of the above modes are active. This situation requires
special attention if code needs be downloaded during the warm reset.
Note that while Halt Mode is active, reset can invalidate the main instruction cache.
Thus debug handler code downloaded during reset can only be loaded into the mini
instruction cache. However, code can be dynamically downloaded into the main
instruction cache. (refer to
The following sections describe the steps necessary to ensure code is correctly
downloaded into the instruction cache.
3.6.14.4.1 Loading IC During Cold Reset for Debug
The Figure 24
during a cold reset for debug.
Note: In the Figure 24
JTAG IR contains the SELDCSR instruction, the hold_rst signal is set to the value
scanned into DBG_SR[1].
Note: In the Figure 24
pin.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
"Dynamically Loading IC After Reset" on page
shows the actions necessary to download code into the instruction cache
hold_rst is a signal that gets set and cleared through JTAG When the
TRST is an internal signal, it is the inverted value of the JTG_TRST_N
Intel
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
147).
Developer's Manual
143