Example Case 2A - Software Scheduling Sitds For An In Endpoint - Intel IXP45X Developer's Manual

Intel
Table 184.

Example Case 2a - Software Scheduling siTDs for an IN Endpoint

siTD
#
X
X+1
X+2
X+3
This example shows the first three siTDs for the transaction stream. Since this is the
case-2a frame-wrap case, S-masks of all siTDs for this endpoint have a value of 10h (a
one bit in micro-frame 4) and C-mask value of C3h (one-bits in micro-frames 0,1, 6
and 7). Additionally, software ensures that the Back Pointer field of each siTD
references the appropriate siTD data structure (and the Back Pointer T-bits are set to
zero).
The initial SplitXState of the first siTD is Do Start Split. The host controller will visit
the first siTD eight times during frame X. The C-mask bits in micro-frames 0 and 1 are
ignored because the state is Do Start Split. During micro-frame 4, the host controller
determines that it can run a start-split (and does) and changes SplitXState to Do
Complete Split. During micro-frames 6 and 7, the host controller executes complete-
splits. Notice the siTD for frame X+1 has it's SplitXState initialized to Do Complete
Split. As the host controller continues to traverse the schedule during H-Frame X+1, it
will visit the second siTD eight times. During micro-frames 0 and 1 it will detect that it
must execute complete-splits.
During H-Frame X+1, micro-frame 0, the host controller detects that siTD
Pointer.T-bit is a zero, saves the state of siTD
complete split transaction using the transaction state of siTD
transaction is complete, siTD's Active bit is set to zero and results written back to
siTD . The host controller retains the fact that siTD
X
SplitXState in the siTD
prepared to execute the start-split for siTD
split-transaction completes early (transaction-complete is defined in
Isochronous - Do Complete Split" on page
splits have been executed, the host controller will transition siTD
Start Split early and naturally skip the remaining scheduled complete-split
transactions. For this example, siTD
Frame X+2, micro-frame 1.
During H-Frame X+2, micro-frame 0, the host controller detects that siTD
Pointer.T-bit is a zero, saves the state of siTD
above, it executes another split transaction, receives an MDATA response, updates the
transfer state, but does not modify the Active bit. The host controller returns to the
context of siTD
siTD . S
X+2
During H-Frame X+2, micro-frame 1, the host controller detects siTD
a zero, saves the state of siTD
split transaction, receives a DATA0 response, updates the transfer state and sets the
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
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IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
X
Masks 0 1
S-Mask
C-Mask 1 1
S-Mask
C-Mask 1 1
S-Mask
C-Mask 1 1
S-Mask Repeats previous pattern
C-Mask
to Do Start Split. At this point, the host controller is
X+1
, and traverses it's next pointer without any state change updates to
X+2
X+2
Micro-Frames
2 3 4 5
1
1
1
and fetches siTD
X+1
is retired and transitions the
X
when it reaches micro-frame 4. If the
X+1
476), i.e. before all the scheduled complete-
does not receive a DATA0 response until H-
X+1
and fetches siTD
X+2
and fetches siTD . It executes another complete-
X+1
Initial
SplitXState
6 7
Do Start Split
1 1
Do Complete Split
1 1
Do Complete Split
1 1
Do Complete Split
's Back
X+1
. It executes the
X
. If the siTD split
X X
"Periodic
.SplitXState to Do
X
's Back
X+2
. As described
X+1
's S-mask[0] is
X+2
August 2006
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