Branch Target Buffer; Branch Target Buffer (Btb) Operation - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
Example 7. Locking Code into the Cache
lockMe:
mov r0, #5
add r5, r1, r2
. . .
lockMeEnd:
. . .
codeLock:
ldr r0, =(lockMe AND NOT 31); r0 gets a pointer to the first line we
should lock
ldr r1, =(lockMeEnd AND NOT 31); r1 contains a pointer to the last line we
should lock
lockLoop:
mcr p15, 0, r0, c9, c1, 0
cmp r0, r1
add r0, r0, #32
bne lockLoop
The Intel XScale processor provides a global unlock command for the instruction cache.
Writing to coprocessor 15, register 9 unlocks all the locked lines in the instruction
cache and leaves them valid. These lines then become available for the round-robin
replacement algorithm. (See
the exact command.)
3.3

Branch Target Buffer

The Intel XScale processor uses dynamic branch prediction to reduce the penalties
associated with changing the flow of program execution. The Intel XScale processor
features a branch target buffer that provides the instruction cache with the target
address of branch type instructions. The branch target buffer is implemented as a 128-
entry, direct-mapped cache.
This section is primarily for those optimizing their code for performance. An
understanding of the branch target buffer is needed in this case so that code can be
scheduled to best utilize the performance benefits of the branch target buffer.
3.3.1

Branch Target Buffer (BTB) Operation

The BTB stores the history of branches that have executed along with their targets.
Figure 8
previously executed branch and the data contains the target address of the previously
executed branch along with two bits of history information.
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
; This is the code that will be locked into the cache
; here is the code to lock the "lockMe" routine
; lock next line of code into ICache
; are we done yet?
; advance pointer to next line
; if not done, do the next line
Table 22, "Cache Lock-Down Functions" on page 105
shows an entry in the BTB, where the tag is the instruction address of a
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
for
Developer's Manual
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