Performance Monitoring Registers; Clock And Power Management Registers; Cp14 Registers; Accessing The Performance Monitoring Registers - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
Table 29.

CP14 Registers

Performance Monitoring
Clock and Power Management
Software Debug
All other registers are reserved in CP14. Reading and writing them yields unpredictable
results.
3.5.2.1

Performance Monitoring Registers

The performance monitoring unit contains a control register (PMNC), a clock counter
(CCNT), interrupt enable register (INTEN), overflow flag register (FLAG), event
selection register (EVTSEL) and four event counters (PMN0 through PMN3). The format
of these registers can be found in
description on how to use the performance monitoring facility.
Opcode_2 should be zero on all accesses.
These registers can't be accessed by LDC and STC coprocessor instructions.
Table 30.

Accessing the Performance Monitoring Registers

(PMNC) Performance Monitor Control
Register
(CCNT) Clock Counter Register
(INTEN) Interrupt Enable Register
(FLAG) Overflow Flag Register
(EVTSEL) Event Selection Register
(PMN0) Performance Count Register 0
(PMN1) Performance Count Register 1
(PMN2) Performance Count Register 2
(PMN3) Performance Count Register 3
3.5.2.2

Clock and Power Management Registers

These registers contain functions for managing the core clock and power.
For the IXP45X/IXP46X network processors, these registers are not implemented and
reserved for future use.
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
Description
Read / Write
Read / Write
Read / Write
Description
Access Register# (CRn)
0,1,4,5,8
8-15
"Performance Monitoring" on page
CRn CRm
Register Register
# #
0b0000 0b0001
0b0001 0b0001
0b0100 0b0001
0b0101 0b0001
0b1000 0b0001
0b0000 0b0010
0b0001 0b0010
0b0010 0b0010
0b0011 0b0010
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Register# (CRm)
1
0-3 2
6-7 0
0
157, along with a
Instruction
Read: MRC p14, 0, Rd, c0, c1, 0
Write: MCR p14, 0, Rd, c0, c1, 0
Read: MRC p14, 0, Rd, c1, c1, 0
Write: MCR p14, 0, Rd, c1, c1, 0
Read: MRC p14, 0, Rd, c4, c1, 0
Write: MCR p14, 0, Rd, c4, c1, 0
Read: MRC p14, 0, Rd, c5, c1, 0
Write: MCR p14, 0, Rd, c5, c1, 0
Read: MRC p14, 0, Rd, c8, c1, 0
Write: MCR p14, 0, Rd, c8, c1, 0
Read: MRC p14, 0, Rd, c0, c2, 0
Write: MCR p14, 0, Rd, c0, c2, 0
Read: MRC p14, 0, Rd, c1, c2, 0
Write: MCR p14, 0, Rd, c1, c2, 0
Read: MRC p14, 0, Rd, c2, c2, 0
Write: MCR p14, 0, Rd, c2, c2, 0
Read: MRC p14, 0, Rd, c3, c2, 0
Write: MCR p14, 0, Rd, c3, c2, 0
Developer's Manual
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