Seldcsr Jtag Command; Seldcsr Jtag Register; Seldcsr Hardware - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
3.6.11.1

SELDCSR JTAG Command

The 'SELDCSR' JTAG instruction selects the DCSR JTAG data register. The JTAG op code
is '01001'. When the SELDCSR JTAG instruction is in the JTAG instruction register, the
debugger can directly access the Debug Control and Status Register (DCSR). The
debugger can only modify certain bits through JTAG, but can read the entire register.
The SELDCSR instruction also allows the debugger to generate an external debug
break.
3.6.11.2

SELDCSR JTAG Register

Placing the "SELDCSR" JTAG instruction in the JTAG IR, selects the DCSR JTAG Data
register
debug break, set the hold_rst signal, which is used when loading code into the
instruction cache during reset.
Figure 13.

SELDCSR Hardware

A Capture_DR loads the current DCSR value into DBG_SR[34:3]. The other bits in
DBG_SR are loaded as shown in
A new DCSR value can be scanned into DBG_SR, and the previous value out, during the
Shift_DR state. When scanning in a new DCSR value into the DBG_SR, care must be
taken to also set up DBG_SR[2:1] to prevent undesirable behavior.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
(Figure 13), allowing the debugger to access the DCSR, generate an external
TDI
ignored
TCK
Core CLK
0
35 34
34 33
external debug break
31
software read/write
Figure 13.
® ®
Intel IXP45X and Intel
Capture_DR
0 1 0
TDO
DBG_SR
3 2 1 0
Update_DR
DBG_REG
2 1 0
hold_rst
DCSR
0
IXP46X Product Line of Network Processors
Developer's Manual
B4338-01
125