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®
Memory Controller—Intel
11.3
Power Failure Mode
This mode is not supported by the IXP45X/IXP46X network processors as there is no
support for self-refresh.
11.4
Interrupts/Error Conditions
The MCU has two conditions which require intervention from the Intel XScale
processor. If a single-bit error is detected during a read cycle, the MCU can correct the
data returned but software needs to fix the error in the memory array. If a multi-bit
error is detected, the core decides how to handle the condition. For all ECC errors, the
MCU records the requester of the transaction resulting in the error in ELOGx[23:16]
and interrupts the core.
If the MCU detects an ECC error during a read or write cycle
set to 1. Whenever the MCU toggles one of the MCISR bits from 0 to 1, an interrupt is
generated to the core.
Table 214
Table 214.
MCU Error Response
Single-Bit during a read or write
Multi-bit during a read
Multi-bit during a write
1. The ECC Enable bit in the ECCR needs to be set in order for these actions to occur.
Note:
If ECC reporting is enabled with ECCR[1] or ECCR[0] and an ECC error occurs,
MCISR[1] or MCISR[0] is set and ELOGx/ECARx logs the error in addition to the actions
in
Table
1. Any error condition during a write cycle actually occurs while performing the read portion of a
read-modify-write on a partial write. See
August 2006
Order Number: 306262-004US
®
IXP45X and Intel
IXP46X Product Line of Network Processors
shows how the MCU responds to error conditions.
Error Type
214.
Fix Error (if ECC error correction is enabled in the ECCR)
Interrupt the Intel XScale
Controller
or
Terminate the Core transaction, notify the BIU of multi-bit error
New ECC is generated with bad data and written to DDRI SDRAM
array. Data location is no longer valid.
"ECC Generation" on page 615
®
®
Intel
IXP45X and Intel
1
, MCISR[0] or MCISR[1] is
1
MCU Action
®
Processor through the Interrupt
for details.
IXP46X Product Line of Network Processors
Developer's Manual
627
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