Code Download During A Warm Reset For Debug - Intel IXP45X Developer's Manual

Intel
Figure 25.

Code Download During a Warm Reset For Debug

Reset pin
TRST
Internal
RESET
hold_rst
JTAG IR JTAG INSTR
Halt Mode
As shown in
processor is in Halt Mode. Since the instruction cache was not invalidated, it may
contain valid lines. The host must avoid downloading code to virtual addresses that are
already valid in the instruction cache (mini IC or main IC), otherwise the processor may
behave unpredictably.
There are several possible solutions that ensure code is not downloaded to a VA that
already exists in the instruction cache.
Since the mini instruction cache was not invalidated, any code previously downloaded
into the mini IC is valid in the mini IC, so it is not necessary to download the same code
again.
If it is necessary to download code into the instruction cache:
1. Assert TRST.
This clears the Halt Mode bit allowing the instruction cache to be invalidated.
2. Clear the Halt Mode bit through JTAG.
This allows the instruction cache to be invalidated by reset.
3. Place the LDIC JTAG instruction in the JTAG IR, then proceed with the normal code
download, using the Invalidate IC Line function before loading each line.
This requires 10 packets to be downloaded per cache line instead of the 9 packets
described in
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
146
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
RESET pin asserted until hold_rst signal is set
RESET does not affect Mini IC (Halt Mode Bit set)
hold_rst keeps internal reset asserted
SELDCSR
set hold_rst signal
keep Halt Mode bit set
Figure 25, reset does not invalidate the instruction cache because of the
"LDIC Cache Functions" on page 141
clock 15 tcks after
last update_dr
wait 2030 tcks after
in LDIC mode
Reset deasserted
LDIC
enter LDIC mode
Load code into IC
®
Processor
SELDCSR
clear hold_rst signal
keep Halt Mode bit set
B4352-01
August 2006
Order Number: 306262-004US