Scheduling Multiply Instructions - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
All data processing instructions incur a two cycle issue penalty and a two-cycle result
penalty when the shifter operand is a shift/rotate by a register or shifter operand is
RRX. Since the next instruction would always incur a 2 cycle issue penalty, there is no
way to avoid such a stall except by re-writing the assembler instruction. Consider the
following segment of code:
mov
mul
add
sub
The subtract instruction would incur a one-cycle stall due to the issue latency of the
add instruction as the shifter operand is shift by a register. The issue latency can be
avoided by changing the code as follows:
mov
mul
add
sub
3.10.5.3

Scheduling Multiply Instructions

Multiply instructions can cause pipeline stalls due to either resource conflicts or result
latencies. The following code segment would incur a stall of zero to three cycles
depending on the values in registers r1, r2, r4 and r5 due to resource conflicts.
mul
mul
The following code segment would incur a stall of one to three cycles, depending on the
values in registers r1 and r2 due to result latency.
mul
mov
Note that a multiply instruction that sets the condition codes blocks the whole pipeline.
A four-cycle multiply operation that sets the condition codes behaves the same as a 4
cycle issue operation. Consider the following code segment:
muls
add
sub
sub
The add operation above would stall for three cycles if the multiply takes four cycles to
complete. It is better to replace the code segment above with the following sequence:
mul
add
sub
sub
cmp
Please refer to
various multiply instructions. The multiply instructions should be scheduled taking into
consideration these instruction latencies.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
r3, #10
r4, r2, r3
r5, r6, r2, LSL r3
r7, r8, r2
r3, #10
r4, r2, r3
r5, r6, r2, LSL #10
r7, r8, r2
r0, r1, r2
r3, r4, r5
r0, r1, r2
r4, r0
r0, r1, r2
r3, r3, #1
r4, r4, #1
r5, r5, #1
r0, r1, r2
r3, r3, #1
r4, r4, #1
r5, r5, #1
r0, #0
"Instruction Latencies" on page 182
Intel
to get the instruction latencies for
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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