Aqm Sram - Intel IXP45X Developer's Manual

AHB Queue Manager (AQM)—Intel
Processors
If this bit is set to 1, then the interrupts will only reset if the interrupting condition has
also been cleared when the write to the QUEINTREG occurs. In other words, this bit
determines if the interrupt is globally rising edge sensitive (INT0SCRSELREG0[3] is '0')
or is level sensitive (INT0SCRSELREG0[3] is '1'). In addition, the interrupt mask is
applied after the interrupt register. This means that the QUEINTREG register will reflect
the active status of masked interrupts.
Notice that there is a subtle difference in how the interrupt mask is applied in these two
cases. If the bit is '0' the interrupt mask prevents the setting of the interrupt status
register bit whereas if the bit is '1' the interrupt mask prevents the propagation of the
interrupt status register bit. This introduces a corner case. If the bit is set to a one, an
interrupt is generated on a queue and then that interrupt is subsequently disabled, but
it is either not cleared (because there is no write to QUEINTREG) or is not clearable
(because the condition is still true and in this mode it is level sensitive) then if you
change the mode to '0' the interrupt mask is no longer applied, and a (spurious)
interrupt will be generated. The interrupt itself cannot be prevented, but after the
mode switch the interrupt may be cleared and subsequently will remain masked.
27.4.3

AQM SRAM

The queue buffers and queue configuration words managed by the AQM reside in on-
chip SRAM. The SRAM is a 2K by 36 bits wide implementation (where the "extra" 4 bits
are used for parity protection). It is a single port synchronous SRAM that supports write
accesses and a 133 MHz clock. The SRAM is fully accessible via the AHB interface to the
AQM as well as the queue control for queue access. The queue configuration words are
located in the bottom 64 words of the SRAM with the remainder of the SRAM being
allocated to queue buffers. The SRAM may be freely written and read, although writes
will have obvious side effects. Overwriting the configuration words results in
unpredictable behavior in the queues. Therefore, reads of the SRAM may not
commingle with the normal usage of the queue manager's queues. Reading and writing
the SRAM may either be done as part of a diagnostic test or as part of the normal
operation of the AQM.
The existence of parity requires that the memory be initialized to a defined pattern
before it is read. The SRAM is divided into two regions, the Queue Configuration Words
and the buffer space. Reading a location either directly or by operating the AQM in its
natural mode without initializing the location is most likely going to produce a parity
error. For this reason, software must take care to either initialize the AQM SRAM or
guarantee that no reads are ever performed before a write. To initialize the SRAM for a
strict queue usage model, all that is necessary is to initialize the queue control word for
the specific queue and to guarantee that no reads are done before the first write.
Accessing the SRAM for direct access operations (i.e. addresses > 0x2000) may
produce corner cases where "left over" pointers (from previous operations) to
uninitialized locations cause spurious and hidden reads. For this reason, if the queue
manager SRAM is expected to support direct access operations, the entire SRAM will
have to be initialized to guarantee that no spurious errors will be detected. The "safest"
solution is for the boot software to always initialize the SRAM to a constant value (such
as 0x00000000) after power-up or reset. Parity errors will not be reported if parity
reporting is disabled in the address error register, and this bit should be left in the
disable position until memory is initialized.
A parity error may be signaled via an interrupt to the Intel XScale processor or some
other mechanism. When the Error bit in the QUEADDERR register is true the
aqm_parity_error port is true, and remains true until the Error bit is cleared. There is
little or no recourse for parity errors, and the detection of a parity error indicates that a
fatal and unrecoverable error has occurred in the AQM SRAM. However, the logical
operation of the AQM is marginally intact. Should the parity error occur on a data fetch
only the data is corrupted. Should the parity error occur on a configuration word fetch,
the entire operation of that queue (and whether it interferes with the operation of
another queue) may be compromised. It should be assumed that any parity error
August 2006
Reference Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network
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Intel
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IXP45X and Intel IXP46X Product Line of Network Processors
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