Udc Endpoint 2 Control/Status Register; Receive Fifo Service (Rfs); Receive Packet Complete (Rpc); Bit 2 Reserved - Intel IXP45X Developer's Manual

Bits
31:8
7
6
5
4
3
2
1
0
8.5.4

UDC Endpoint 2 Control/Status Register

The UDC Endpoint 2 Control/Status Register contains seven bits that are used to
operate endpoint 2, a Bulk OUT endpoint.
8.5.4.1

Receive FIFO Service (RFS)

The receive FIFO service bit is set if the receive FIFO has one complete data packet in it
and the packet has been error checked by the UDC. A complete packet may be
64 bytes, a short packet, or a zero packet. This bit is not cleared until all data has been
read from both buffers.
8.5.4.2

Receive Packet Complete (RPC)

The receive packet complete bit is set by the UDC when an OUT packet is received.
When this bit is set, the IR2 bit in the appropriate UDC status/interrupt register is set,
if receive interrupts are enabled.
This bit can be used to validate the other status/error bits in the Endpoint 2 Control/
Status Register. The UDCCS2[RPC] bit is cleared by writing a 1 to it. The UDC issues
NAK handshakes to all OUT tokens while this bit is set and both buffers have unread
data.
8.5.4.3

Bit 2 Reserved

Bit 2 is reserved for future use.
8.5.4.4 Bit 2 Reserved
Bit 3 is reserved for future use.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
298
® ®
Intel IXP45X and Intel
Register
Name
(Reserved)
Transmit short packet (read/write 1 to set).
TSP
1 = Short packet ready for transmission.
(Reserved). Always reads 0.
Force STALL (read/write).
FST
1 = Issue STALL handshakes to IN tokens.
Sent STALL (read/write 1 to clear).
SST
1 = STALL handshake was sent.
Transmit FIFO underrun (read/write 1 to clear)
TUR
1 = Transmit FIFO experienced an underrun.
Flush Tx FIFO (always read 0/ write a 1 to set).
FTF
1 = Flush Contents of TX FIFO
Transmit packet complete (read/write 1 to clear).
TPC 0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
Transmit FIFO service (read-only).
TFS 0 = Transmit FIFO has no room for new data
1 = Transmit FIFO has room for at least 1 complete data packet
IXP46X Product Line of Network Processors—USB 1.1 Device
UDCCS1
Description
Controller
(UDCCS2)
August 2006
Order Number: 306262-004US