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DMA channel is disabled. The second register set may be active and using the DMA
channel when the first DMA has finished.
• One bit to define the byte order of the data transferred.
Bit 28 of the Length Register is used to provide a byte swap on the DMA data as
data is transferred from the AHB to the PCI bus or from the PCI Bus to AHB,
depending upon the direction of the DMA transfer. When bit 28 is set to logic 1, a
byte swap will occur on the DMA data.
DMA transfer byte lane swapping.
Figure 93.
AHB-to-PCI DMA-Transfer Byte Lane Swapping
Figure 94.
PCI-to-AHB DMA-Transfer Byte Lane Swapping
The DMA channels share resources with the AHB Master and Target interfaces and
therefore must arbitrate for these resources. AHB-to-PCI DMA transfers use the AHB
Master Interface, the PCI Initiator Request FIFO, and Initiator Transmit FIFO. PCI-to-
AHB DMA transfers use the AHB Master Interface, the PCI Initiator Request FIFO, and
Initiator Receive FIFO. Use of the AHB Master Interface will revolve between the two
DMA channels and PCI requests that appear in the Target Receive FIFO.
A DMA transfer is started on a particular channel by writing the PCI start address, AHB
start address, and length to one set of DMA CSRs. If the channel enable bit is set in the
length register, that DMA channel is enabled and the transfer is executed. While the
transfer is taking place, the other set of DMA CSRs can be set-up to specify the next
transfer. When the current transfer is complete, the DMA complete bit is set in the
status register and the channel enable bit is cleared in the length register. Execution
then starts using the second set of DMA CSRs, if the channel is enabled in the length
register. Transfers continue in this fashion until the channel enable bits in both sets of
DMA length registers are cleared.
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Develepor's Manual
538
®
®
Intel
IXP45X and Intel
AHB Data
Byte 3
Byte 0
PCI Data
Byte 0
AHB Data
PCI Data
Byte 3
IXP46X Product Line of Network Processors—PCI Controller
Figure 93
and
Figure 94
Byte 2
Byte 1
Byte 1
Byte 2
Byte 1
Byte 2
Byte 2
Byte 1
demonstrates the
Byte 0
Byte 3
B4294-01
Byte 3
Byte 0
B4295-01
August 2006
Order Number: 306262-004US
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