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USB 1.1 Device Controller—Intel
Processors
Register Name:
0 x C800B03C
Hex Offset Address:
Register
Universal Serial Bus Device Controller Endpoint 11 Control and Status Register
Description:
Access: Read/Write
31
Bits
31:8
7
6
5
4
3
2
1
0
8.5.14
UDC Endpoint 12 Control/Status Register
The UDC Endpoint 12 Control/Status Register contains seven bits that are used to
operate endpoint 12, a Bulk OUT endpoint.
8.5.14.1
Receive FIFO Service (RFS)
The receive FIFO service bit is set if the receive FIFO has one complete data packet in it
and the packet has been error checked by the UDC. A complete packet may be
64 bytes, a short packet, or a zero packet.
This bit is not cleared until all data has been read from both buffers.
August 2006
Order Number: 306262--, Revision: 004US
®
®
IXP45X and Intel
IXP46X Product Line of Network
Bits
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
Transmit short packet (read/write 1 to set).
TSP
1 = Short packet ready for transmission.
(Reserved). Always reads 0.
Force STALL (read/write).
FST
1 = Issue STALL handshakes to IN tokens.
Sent STALL (read/write 1 to clear).
SST
1 = STALL handshake was sent.
Transmit FIFO underrun (read/write 1 to clear).
TUR
1 = Transmit FIFO experienced an underrun.
Flush Tx FIFO (always read 0/ write a 1 to set).
FTF
1 = Flush Contents of TX FIFO.
Transmit packet complete (read/write 1 to clear).
TPC
0 = Error/status bits invalid.
1 = Transmit packet has been sent and error/status bits are valid.
Transmit FIFO service (read-only).
TFS
0 = Transmit FIFO has no room for new data.
1 = Transmit FIFO has room for at least 1 complete data packet.
Intel
UDCCS11
0 x 00000001
Reset Hex Value:
UDCCS11
Description
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
(UDCCS12)
Developer's Manual
0
1
319
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