Intel IXP45X Developer's Manual page 5

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Contents-Intel IXP45X and Intel
3.6.4.7
3.6.5 Debug Exceptions................................................................................. 115
3.6.5.1
3.6.5.2
3.6.6 HW Breakpoint Resources...................................................................... 117
3.6.6.1
3.6.6.2
3.6.7 Software Breakpoints............................................................................ 120
3.6.8 Transmit/Receive Control Register .......................................................... 120
3.6.8.1
3.6.8.2
3.6.8.3
3.6.8.4
3.6.8.5
3.6.9 Transmit Register ................................................................................. 124
3.6.10 Receive Register .................................................................................. 124
3.6.11 Debug JTAG Access .............................................................................. 124
3.6.11.1 SELDCSR JTAG Command ........................................................ 125
3.6.11.2 SELDCSR JTAG Register........................................................... 125
3.6.11.3 DBGTX JTAG Command ........................................................... 127
3.6.11.4 DBGTX JTAG Register .............................................................. 127
3.6.11.5 DBGRX JTAG Command ........................................................... 128
3.6.11.6 DBGRX JTAG Register.............................................................. 128
3.6.11.7 Debug JTAG Data Register Reset Values..................................... 132
3.6.12 Trace Buffer ........................................................................................ 132
3.6.12.1 Trace Buffer CP Registers......................................................... 132
3.6.13 Trace Buffer Entries .............................................................................. 134
3.6.13.1 Message Byte ......................................................................... 134
3.6.13.2 Trace Buffer Usage.................................................................. 137
3.6.14 Downloading Code in ICache.................................................................. 139
3.6.14.1 LDIC JTAG Command .............................................................. 139
3.6.14.2 LDIC JTAG Data Register ......................................................... 140
3.6.14.3 LDIC Cache Functions.............................................................. 141
3.6.14.4 Loading IC During Reset .......................................................... 142
3.6.14.5 Dynamically Loading IC After Reset ........................................... 147
3.6.14.6 Mini-Instruction Cache Overview ............................................... 150
3.6.15 Halt Mode Software Protocol .................................................................. 150
3.6.15.1 Starting a Debug Session ......................................................... 150
3.6.15.2 Implementing a Debug Handler ................................................ 152
3.6.15.3 Ending a Debug Session .......................................................... 155
3.6.16 Software Debug Notes and Errata ........................................................... 156
3.7 Performance Monitoring ................................................................................... 157
3.7.1 Overview ............................................................................................ 157
3.7.2 Register Description.............................................................................. 158
3.7.2.1
3.7.2.2
3.7.2.3
3.7.2.4
3.7.2.5
3.7.2.6
3.7.3 Managing the Performance Monitor ......................................................... 162
3.7.4 Performance Monitoring Events .............................................................. 162
3.7.4.1
3.7.4.2
3.7.4.3
3.7.4.4
3.7.4.5
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
Trace Buffer Enable Bit (E) ....................................................... 114
Halt Mode .............................................................................. 115
Monitor Mode ......................................................................... 117
Instruction Breakpoints............................................................ 118
Data Breakpoints .................................................................... 118
RX Register Ready Bit (RR) ...................................................... 121
Overflow Flag (OV) ................................................................. 122
Download Flag (D) .................................................................. 122
TX Register Ready Bit (TR)....................................................... 123
Conditional Execution Using TXRXCTRL ...................................... 123
Clock Counter (CCNT) ............................................................. 158
Performance Count Registers.................................................... 158
Performance Monitor Control Register ........................................ 159
Interrupt Enable Register ......................................................... 159
Overflow Flag Status Register ................................................... 160
Event Select Register .............................................................. 161
Instruction Cache Efficiency Mode ............................................. 163
Data Cache Efficiency Mode...................................................... 163
Instruction Fetch Latency Mode ................................................ 164
Data/Bus Request Buffer Full Mode............................................ 164
Stall/Write-Back Statistics........................................................ 165
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Intel
®
IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
5