Ddri Sdram Mode Programming - Intel IXP45X Developer's Manual

location has a valid ECC byte. The Intel XScale processor processor must be used to fill
the memory array with a constant, thereby initializing the associated ECC bytes in the
process. If the memory array is not initialized, the BIU or PCC may attempt to read
memory locations beyond the specified word(s). In this case, the MCU will report an
ECC error even though software did not specifically request the un-initialized data.
11.2.2.9

DDRI SDRAM Mode Programming

The MCU programs the DDRI SDRAM devices through a mode-register-set command.
During the initialization sequence this command sets the DDRI SDRAM mode register
(see Section 11.2.2.8, "DDRI SDRAM
SDCR[1:0].
The DDRI SDRAM state machine ensures that a row-activate command is issued no
sooner than T
The values to be programmed in the SDCR[1:0] registers are based on the DDRI
SDRAM devices being interfaced to the IXP45X/IXP46X network processors. Because
the parameters that define the time between allowed commands are programmable,
this allows flexibility in the type of DDRI device that is selected, in addition to de-
coupling the hardware to any frequency dependencies.
Note: The MCU_DDRSM will NOT interact properly with the DDRI SDRAM until the SDCR[1:0]
registers have been programmed.
The duration between valid commands must be programmed by the user before the
DDRSM can interact properly with the DDRI. These parameters are defined by either
JEDEC and/or within this document in the timing diagrams and equations in
11.6.2, "DDRI SDRAM Control Register 0 SDCR0"
Control Register 1
The timing parameters for all non-read and non-write commands are derived directly
from the JEDEC Standard Double Data Rate (DDR) SDRAM Specification JESD79, June
2004 and JEDEC DDR - II SDRAM Specification, September 2002. These parameters,
and their relationship to each other, are outlined in
specification for the timing parameters specific to the DDR device that is to be
implemented in the system.
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cycles after the mode-register-set command.
mrd
SDCR1".
IXP46X Product Line of Network Processors—Memory Controller
Initialization") by programming the SDIR and
and
Figure
Section
Section 11.6.3, "DDRI SDRAM
110. Please see the device
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