Intel IXP45X Developer's Manual page 570

10.5.3.18 AHB-to-PCI DMA PCI Address Register 0
Register Name:
Block
0xC00000
Base Address:
Destination address on the PCI bus for AHB-to-PCI DMA transfers.
Paired with pci_atpdma1_pciaddr to allow buffering of DMA
Register Description:
transfer requests.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
31:2 address PCI word address
1:0 Lower PCI address bits hard-wired to zero.
10.5.3.19 AHB-to-PCI DMA Length Register 0
Register Name:
Block
0xC00000
Base Address:
Provides word count and control for AHB-to-PCI DMA transfers.
Paired with pci_atpdma1_length to allow buffering of DMA transfer
Register Description:
requests.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
EN (Rsvd) DS
Register
Bits Name
Channel enable. When set to a 1, executes a DMA transfer if wordcount is
31 EN nonzero. When 0, the channel is disabled. Hardware clears this bit when
the DMA transfer is complete.
30:2
reserved Reserved. Read as 0.
9
Data Swap indicator. When set to a 1, data from the AHB bus is byte
28 DS
swapped before being sent to the PCI bus. When 0, no swapping is done.
27:1
reserved Reserved. Read as 0.
6
15:0 wordcount Number of words to transfer.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Develepor's Manual
570
® ®
Intel IXP45X and Intel
Offset Address
address
Description
Offset Address
(Reserved)
Description
IXP46X Product Line of Network Processors—PCI Controller
pci_atpdma0_pciaddr
0x44
pci_atpdma0_pciaddr
pci_atpdma0_length
0x48
Wordcount
pci_atpdma0_length
0x00000000
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
0
Reset PCI AHB
Value Access Access
0x0000
RO
0000
00 RO
0x00000000
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
Reset PCI AHB
Value Access Access
0 RO
00 RO
0 RO
0x000 RO
0x0000 RO
August 2006
Order Number: 306262-004US
0
0
RW
RO
0
RW
RO
RW
RO
RW