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®
Ethernet MACs—Intel
IXP45X and Intel
6.2.7
Transmit Control 1
Register Name:
0xC8009000
Hex Offset Address:
Register
Transmit Control Register
Description:
Access: Read/Write.
31
Bits
31:7
6
5
4
3
2
1
0
6.2.8
Transmit Control 2
Register Name:
0xC8009004
Hex Offset Address:
Register
Transmit Control Register
Description:
Access: Read/Write.
31
Bits
4:31
3:0
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
(Reserved)
Register
Name
(Reserved)
MII config
0 = Configures the PHY interface as a MII.
Two-part
1 = Causes the optional two part deferral to be used.
deferral
1 = Causes FCS to be computed and appended to transmit frames before they
Append FCS
are sent to the PHY.
1 = Causes transmit frames less than to minimum frame size to be padded
Pad enable
before they are sent to the PHY.
1 = Causes transmit frames to be retried until the maximum retry limit shown in
Retry enable
the Transmit Control 2 Register is reached, when collisions occur.
1 = Half-duplex operation
Half duplex
0 = Full-duplex
Transmit
1 = Causes transmission to be enabled.
enable
(Reserved)
Register
Name
(Reserved)
Maximum retries
Maximum number of retries for a packet when collisions occur.
Intel
txctrl1
0x00000000
Reset Hex Value:
txctrl1
Description
txcrtl2
0x00000000
Reset Hex Value:
txcrtl2
Description
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
7
6
5
4
3
2
1
0
4
3
0
Maximum
Retries
Developer's Manual
249
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