Instruction-Cache 'Miss; Instruction Cache Organization - Intel IXP45X Developer's Manual

Intel
memory that contains the requested instruction using the fetch policy described in
"Instruction-Cache 'Miss'" on page
the instructions are placed in one of two fetch buffers and the requested instruction is
delivered to the instruction decoder.
A fetched line will be written into the cache if it is cacheable. Code is designated as
cacheable when the Memory Management Unit (MMU) is disabled or when the MMU is
enable and the cacheable (C) bit is set to 1 in its corresponding page. See
Management Unit" on page 69
Note that an instruction fetch may "miss" the cache but "hit" one of the fetch buffers.
When this happens, the requested instruction will be delivered to the instruction
decoder in the same manner as a cache "hit."
Figure 6.

Instruction Cache Organization

Example: 32-Kbyte cache
Set Index
This example
shows Set 0 being
selected by the
set index.
Tag
Word Select
Disabling the cache prevents any lines from being written into the instruction cache.
Although the cache is disabled, it is still accessed and may generate a "hit" if the data is
already in the cache.
Disabling the instruction cache does not disable instruction buffering that may occur
within the instruction fetch buffers. Two 8-word instruction fetch buffers will always be
enabled in the cache disabled mode. So long as instruction fetches continue to "hit"
within either buffer (even in the presence of forward and backward branches), no
external fetches for instructions are generated. A miss causes one or the other buffer to
be filled from external memory using the fill policy described in
'Miss'" on page
3.2.1.1

Instruction-Cache 'Miss'

An instruction-cache "miss" occurs when the requested instruction is not found in the
instruction fetch buffers or instruction cache; a fetch request is then made to external
memory. The instruction cache can handle up to two "misses." Each external fetch
request uses a fetch buffer that holds 32-bytes and eight valid bits, one for each word.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
78
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
for a discussion on page attributes.
Set 1
way 0
Set 0
way 1
way 0
way 1
CAM
CAM
way 31
way 31
78.
78. As the fetch returns instructions to the cache,
Set 31
way 0
way 1
CAM
8 Words (cache line)
8 Words (cache line) way 31
DATA
DATA
Instruction Word
(4 bytes)
®
Processor
"Memory
8 Words (cache line)
DATA
CAM: Content
Addressable Memory
B4328-01
"Instruction-Cache
August 2006
Order Number: 306262-004US