Ahb Queue Manager Memory Map; Ahb Interface - Intel IXP45X Developer's Manual

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are necessarily constrained to occur in the order they occur on the AHB. The timing
between an AHB operation and a flag bus update is fixed. Not all NPEs are required to
be connected to the flag bus via their CCP, so this connection scheme is very flexible.
The event outputs are also connected to the NPE CCP and wired to the appropriate
events as the top level system requires. Each AQM produces three event outputs 'A', 'B'
and 'C'.
27.4

AHB Interface

The AHB interface provides read/write access to all AQM configuration/status registers,
queues and SRAM. The AQM is a slave with a 32 bit data bus configuration on the AHB.
The address map for the AQM is shown in
are relative offsets from the from the AQM base address. Unsupported exceptions to
the AHB slave requirements include accesses with a data transfer size of byte or half-
word, wrapping burst accesses and 16 beat incrementing burst accesses. These
accesses will result in an AHB Error response. Accesses to any unused locations within
the AQM address space will result in an OKAY response on the AHB. Read accesses to
the unused address locations will result in zeroes returned on the AHB. The AQM will
not perform any internal operations on write accesses to any unused locations. Data
formats for all registers accessible via the AHB is given in
Descriptions" on page
Table 293. AHB Queue Manager Memory Map (Sheet 1 of 2)
Address
0x03FFC
0x02100
0x020FC
0x02000
0x01FFC
0x00468
0x00464
0x00460
0x0045C
0x00458
0x00454
0x00450
0x0044C
0x00448
0x00444
0x00440
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
928
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IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager
939.
64 Queue Buffer Space - SRAM
64 Queue Configuration Words - SRAM
Queue 0 to 31 Status Map Register
Queue 32 to 63 Event Source Register
Queue 32 to 63 Event 'C' Enable Register
Queue 32 to 63 Event 'B' Enable Register
Queue 32 to 63 Event 'A' Enable Register
Queue 32 to 63 Nearly Full Status Register
Queue 32 to 63 Empty Status Register
Table 293, the addresses listed in the table
AQM Function
1,984 x 4 Bytes
64 x 4 Bytes
UNUSED ADDRESS SPACE
Reserved
Error Control Register
Reserved
Section 27.6, "Register
August 2006
Reference Number: 306262-004US
(AQM)