Intel IXP45X Developer's Manual page 26

22 LDIC JTAG Data Register Hardware ........................................................................... 140
23 Format of LDIC Cache Functions ............................................................................... 142
24 Code Download During a Cold Reset For Debug .......................................................... 144
25 Code Download During a Warm Reset For Debug ........................................................ 146
26 Downloading Code in IC During Program Execution ..................................................... 147
27 RISC Super-Pipeline................................................................................................ 191
28 Multiple Ethernet PHYS Connected to Processor .......................................................... 229
29 Ethernet Coprocessor Interface ................................................................................ 230
30 MDIO Write ........................................................................................................... 232
31 MDIO Read ............................................................................................................ 233
32 UTOPIA Level 2 Coprocessor .................................................................................... 269
33 UTOPIA Level 2 MPHY Transmit Polling ...................................................................... 271
34 UTOPIA Level 2 MPHY Receive Polling ........................................................................ 274
35 NRZI Bit Encoding Example...................................................................................... 282
36 Example USB 2.0 System Configuration..................................................................... 354
37 Top-Level Block Diagram ......................................................................................... 355
38 Periodic Schedule Organization................................................................................. 356
39 Asynchronous Schedule Organization ........................................................................ 357
40 Block Diagram ....................................................................................................... 358
41 Microprocessor Interface Block Diagram .................................................................... 359
42 DMA Engine Block Diagram ...................................................................................... 360
43 Protocol Engine Block Diagram ................................................................................. 361
44 Port Controller Block Diagram .................................................................................. 362
45 Periodic Schedule Organization................................................................................. 390
46 Asynchronous Schedule Organization ........................................................................ 391
47 Isochronous Transaction Descriptor (iTD) .................................................................. 392
48 Split-transaction Isochronous Transaction Descriptor (siTD) ......................................... 395
49 Queue Element Transfer Descriptor Block Diagram...................................................... 399
50 Queue Head Structure Layout .................................................................................. 404
51 Frame Span Traversal Node Structure Layout ............................................................. 408
52 Example USB 2.0 Host Controller Port Routing Block Diagram....................................... 411
53 Port Owner Hand-Off State Machine .......................................................................... 414
54 Derivation of Pointer into Frame List Array ................................................................. 419
55 General Format of Asynchronous Schedule List ........................................................... 419
56 Best Fit Approximation ............................................................................................ 421
57 Frame Boundary Relationship between HS bus and FS/LS Bus ...................................... 423
58 Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries ................ 424
59 Example Periodic Schedule ...................................................................................... 426
60 Example Association of iTDs to Client Request Buffer................................................... 429
61 Generic Queue Head Unlink Scenario......................................................................... 434
62 Asynchronous Schedule List with Annotation to Mark Head of List ................................. 435
63 Example State Machine for Managing Asynchronous Schedule Traversal......................... 436
64 Example HC State Machine for Controlling Nak Counter Reloads.................................... 440
65 Host Controller Queue Head Traversal State Machine................................................... 442
66 Example Mapping of qTD Buffer Pointers to Buffer Pages ............................................. 450
67 Host Controller Asynchronous Schedule Split-Transaction State Machine ........................ 454
68 Split Transaction, Interrupt Scheduling Boundary Conditions ........................................ 456
69 General Structure of EHCI Periodic Schedule Utilizing Interrupt Spreading ...................... 457
70 Example Host Controller Traversal of Recovery Path via FSTNs ..................................... 459
71 Split Transaction State Machine for Interrupt.............................................................. 463
72 Split Transaction, Isochronous Scheduling Boundary Conditions .................................... 469
73 siTD Scheduling Boundary Examples ......................................................................... 471
74 Split Transaction State Machine for Isochronous ......................................................... 474
75 PCI Bus Configured as a Host ................................................................................... 496
76 PCI Bus Configured as an Option .............................................................................. 496
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
26
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Intel IXP45X and Intel IXP46X Product Line of Network Processors-Contents
August 2006
Order Number: 306262-004US