Hardware Model; Block Diagram - Intel IXP45X Developer's Manual

Intel
9.6.3

Hardware Model

9.6.3.1

Block Diagram

Figure 40.

Block Diagram

® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
358
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
System Bus Slave Interface
Microprocessor
Slave Interface
•
Bus Interface
•
Control and Status
Registers
•
Interrupt Generation
System Bus Master Interface
DMA Engine
•
Bus Interface
•
Host: Transversal State Machine
•
Device: Endpoint Priming State Machine
•
Data Movement
Dual Port RAM Contoller
•
Single channel (for host)
•
Virtual FIFO channels (for device)
•
DMA Contexts
On-Chip Dual Port
Synchronous SRAM
Protocol Engine
•
Interval Timers
•
Error Handing
•
CRC handling
•
Bus handshake generation
Port Controllers
•
Port Status and Control
•
Asynchronous clock domain crossing
•
Transceiver Interface Logic
USB 2.0 Physical Layer Interface
Order Number: 306262-004US
B4198-01
August 2006