List Of Features - Intel IXP45X Developer's Manual

On the first level, the PCI Target Interface requests and the DMA requests alternate for
priority access. On the first transaction the PCI Target interface would gain access to
the South AHB Master Controller's services, followed by one of the DMA channels
gaining access to the South AHB Master Controller's services, then the PCI Target
interface would gain access to the South AHB Master Controller's services again,
followed by the second DMA channel gaining access to the South AHB Master
Controller's services, etc.
On the second level of arbitration for the South AHB Master Controller's services, the
two DMA channels will alternate for priority access. DMA channel 0 would gain access
to the South AHB Master Controller's services first, followed by DMA channel 1, and
then DMA channel 0, etc. This arbitration scheme balances the high-bandwidth DMA
traffic with what should be lower bandwidth PCI Target Interface traffic and is only used
in cases where contention exists. For instance, if there are only PCI Target Interface
requests being received by the South AHB Master Controller. The PCI Target would
continually get access to the South AHB Master Controller until a DMA request is
detected.
The PCI Controller also contains two configuration spaces. The PCI Controller Control
and Status Register (CSR) configuration space is used to configure the PCI Controller,
initiate single cycle PCI transactions using the non-pre-fetch registers, operate the DMA
channels, report PCI Controller status, and allow access to the PCI Controller PCI
Configuration Registers. The PCI Configuration Space is a 64-byte, PCI type-0
configuration space that supports a single function.
The PCI Configuration Space can be written or read using registers defined in the
Control and Status Registers when the IXP45X/IXP46X network processors are
configured as a PCI Host. An external PCI Master using PCI Configuration Cycles can
write or read the PCI Configuration Space when the IXP45X/IXP46X network processors
are configured as an Option. The PCI Configuration Space may be accessed by the Intel
XScale processor or the PCI bus but never by both at the same time.
10.2.1

List of Features

• Conforms to PCI Local Bus Specification Revision 2.2
• 32-bit, 0-66MHz PCI bus operation
• Provides initiator (master) and target (slave) PCI interfaces
• Provides AHB-to-PCI and PCI-to-AHB DMA channels
• Includes PCI bus arbiter supporting up to 4 external PCI masters using round-robin
arbitration.
• Access to PCI Configuration registers from PCI or AHB busses
• Provides interrupt to processor to indicate transaction errors on the PCI or AHB bus
• Provides interrupt to processor for DMA complete and DMA error
• Provides doorbell interrupt generation capability to PCI and AHB agents
• Byte, half word, word single reads/writes, burst word reads/writes supported on
AHB and PCI busses
• Generates memory, I/O, and configuration cycles as PCI master
• Provides AHB masters with full access to the 4Gbyte PCI address space, via DMA
channels and/or non-prefetch transactions.
• Provides PCI-to-AHB address translation to map PCI accesses to AHB address space
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Develepor's Manual
500
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller
August 2006
Order Number: 306262-004US