Intel IXP45X Developer's Manual page 314

8.5.11.5 Bit 4 Reserved
Bit 4 is reserved for future use.
8.5.11.6 Bit 5 Reserved
Bit 5 is reserved for future use.
8.5.11.7 Receive FIFO Not Empty (RNE)
The receive FIFO not empty bit indicates that the receive FIFO has unread data in it.
When the UDCCS9[RPC] bit is set, this bit must be read to determine if there is any
data in the FIFO that Intel XScale processor did not read.
The receive FIFO must continue to be read until this bit clears or data will be lost.
8.5.11.8 Receive Short Packet (RSP)
The receive short packet bit is used by the UDC to indicate that the received OUT
packet in the active buffer currently being read is a short packet or zero-sized packet.
This bit is updated by the UDC after the last byte is read from the active buffer and
reflects the status of the new active buffer.
If UDCCS9[RSP] is a one and UDCCS9[RNE] is a 0, it indicates a zero-length packet. If
a zero-length packet is present, the Intel XScale processor must not read the data
register.
UDCCS9[RSP] clears when the next OUT packet is received.
Register Name:
0x C800B034
Hex Offset Address:
Register
Universal Serial Bus Device Controller Endpoint 9Control and Status Register
Description:
Access: Read/Write
31
Bits
31:8
7
6
5
4
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
314
® ®
Intel IXP45X and Intel
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
Receive short packet (read only).
RSP
1 = Short packet received and ready for reading.
Receive FIFO not empty (read-only).
RNE 0 = Receive FIFO empty.
1 = Receive FIFO not empty.
(Reserved). Always reads 0.
(Reserved). Always reads 0.
IXP46X Product Line of Network Processors—USB 1.1 Device
UDCCS9
0x00000000
Reset Hex Value:
Bits
UDCCS9
(Sheet 1 of 2)
Description
Controller
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0
August 2006
Order Number: 306262-004US
0
0