Csr Address Map; Pci Controller Configuration And Status Registers (Csrs) - Intel IXP45X Developer's Manual

Register
Bits Name
31:1
reserved Reserved
6
Specifies value for the Retry timer. Specifies the maximum number of
retries the Master Interface will accept before terminating the transaction.
15:8 RetryTO
A value of 0 disables the timer and allows an unlimited number of Retry
responses.
Specifies value for the TRDY timer. Specifies the number of PCI clocks the
Master Interface will wait before terminating a transfer with Master Abort
7:0 TRDYTO when a target accepts a transaction by asserting PCI_DEVSEL_N but does
not assert PCI_TRDY_N or PCI_STOP_N. A value of 0 disables the timer
and the Master Interface will wait indefinitely for the Target to respond.
10.5.3

PCI Controller Configuration and Status Registers (CSRs)

These registers are accessible from the AHB bus and are memory mapped in the AHB
address space. When the arbs_hsel_ppc_mmr is asserted, the lower AHB address bits
select the accessed register. Registers are byte writable with individual bytes addressed
according to the endianness setting of the AHB bus in pci_csr.ABE.
address map for the CSRs. The AHB offset is relative to the base address for PCI
Controller memory mapped registers in the AHB address space. The PCI offset is
relative to the base address in pci_bar4 for accesses from the PCI bus. Byte addressing
from PCI uses the PCI byte enable convention.
Table 201. CSR Address Map (Sheet 1 of 2)
AHB PCI
Register Name
Offset Offset
0x00 0x00 pci_np_ad
0x04 0x04 pci_np_cbe
0x08 0x08 pci_np_wdata
0x0c 0x0c pci_np_rdata
0x10 0x10 pci_crp_ad_cbe
0x14 0x14 pci_crp_wdata
0x18 0x18 pci_crp_rdata
0x1c 0x1c pci_csr
0x20 0x20 pci_isr
0x24 0x24 pci_inten
0x28 0x28 pci_dmactrl
0x2c 0x2c pci_ahbmembase
0x30 0x30 pci_ahbiobase
0x34 0x34 pci_ahbmembase
0x38 0x38 pci_ahbdoorbell
0x3c 0x3c pci_pcidoorbell
0x40 0x40 pci_atpdma0_ahbaddr
0x44 0x44 pci_atpdma0_pciaddr
0x48 0x48 pci_atpdma0_length
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Develepor's Manual
558
® ®
Intel IXP45X and Intel
Description
PCI non-prefetch address register
PCI non-prefetch command/byte enables register
PCI non-prefetch write data register
PCI non-prefetch read data register
PCI configuration port address/cmd/byte enables
register
PCI configuration port write data register
PCI configuration port read data register
PCI Controller Control and Status register
PCI Controller Interrupt Status register
PCI Controller Interrupt Enable register
DMA control register
AHB Memory Base Address Register
AHB I/O Base Address Register
PCI Memory Base Address Register
AHB Doorbell Register
PCI Doorbell Register
AHB-to-PCI DMA AHB Address Register 0
AHB-to-PCI DMA PCI Address Register 0
AHB-to-PCI DMA Length Register 0
IXP46X Product Line of Network Processors—PCI Controller
pci_rtotto
Description
Reset PCI AHB
Value Access Access
0x00 RO RO
0x80 RW RW
0x80 RW RW
Table 201 shows the
Reset Value Page
0x00000000 559
0x00000000 559
0x00000000 560
0x00000000 560
0x00000000 561
0x00000000 562
0x00000000 562
0x0000000x 563
0x00000000 564
0x00000000 565
0x00000000 565
0xc0000000 566
0x00000000 567
0x00000000 566
0x00000000 568
0x00000000 569
0x00000000 569
0x00000000 570
0x00000000 570
August 2006
Order Number: 306262-004US