Pci Controller Non-Prefetch Write Data Register; Pci Controller Non-Prefetch Read Data Register - Intel IXP45X Developer's Manual

Register
Bits Name
31:8 reserved reserved – read as 0
Byte enables driven onto the PCI_CBE_N[3:0] lines of the PCI bus during
7:4 NP_BE
the data phase of the non-prefetch PCI access.
PCI command driven onto the PCI_CBE_N[3:0] lines of the PCI bus during
3:0 NP_CMD
the address phase of the non-prefetch PCI access.
10.5.3.3

PCI Controller Non-Prefetch Write Data Register

Register Name:
Block
0xC00000
Base Address:
PCI non-prefetch access write data register. Provides write data for
Register Description:
CSR-initiated non-prefetch PCI write access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
31:0 np_wdata Write data for the non-prefetch PCI write cycle.
10.5.3.4

PCI Controller Non-Prefetch Read Data Register

Register Name:
Block
0xC00000
Base Address:
PCI non-prefetch access read data register. Holds read data from
Register Description:
the CSR-initiated non-prefetch PCI read access.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
31:0 np_rdata Read data from the non-prefetch PCI read cycle.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Develepor's Manual
560
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Intel IXP45X and Intel
Description
Offset Address
np_wdata
Description
Offset Address
np_rdata
Description
IXP46X Product Line of Network Processors—PCI Controller
pci_np_cbe
pci_np_wdata
0x08
pci_np_wdata
pci_np_rdata
0x0c
pci_np_rdata
Reset PCI AHB
Value Access Access
0x0000
none
00
0x0 none
0x0 none
0x00000000
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
Reset PCI AHB
Value Access Access
0x0000
none
0000
0x00000000
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
Reset PCI AHB
Value Access Access
0x00000000 none
August 2006
Order Number: 306262-004US
RW
RW
RW
0
RW
0
RO