Overview; Ahb Queue Manager (Aqm) - Intel IXP45X Developer's Manual

Intel
27.0

AHB Queue Manager (AQM)

27.1

Overview

The AHB Queue Manager (AQM) provides queue functionality for various cores. It
maintains the queues as circular buffers in an embedded, 8-Kbyte SRAM. It also
implements the status flags and pointers required for each queue.
The AQM manages 64 independent queues. Each queue is configurable for buffer and
entry size. Additionally status flags are maintained for each queue.
The AQM interfaces include an Advanced High-performance Bus (AHB) interface to the
NPEs and Intel XScale processor (or any other AHB bus master), a Flag Bus interface,
an event bus (to the NPE condition select logic) and two interrupts to the Intel XScale
processor. The AHB interface is used for configuration of the AQM and provides access
to queues, queue status and SRAM. Individual queue status for queues 0-31 is
communicated to the NPEs via the flag bus. Combined queue status for queues 32-63
are communicated to the NPEs via the event bus. The two interrupts, one for queues 0-
31 and one for queues 32-63, provide status interrupts to the Intel XScale processor.
Read or write entries to a queue, will be accomplished by performing AHB read/write
accesses to any of the corresponding Queue Access Register addresses. The AQM will
intercept these accesses, since no physical data resides at these addresses, and lookup
the appropriate queue pointer to perform the requested read or write. Upon a read or
write access to a queue, the pointers and status for the queue are updated as needed.
Further detail is given in the following sections.
The lower queues provide individual status to the NPE Condition Coprocessor (CCP) via
the flag bus interface. This means that any of these queues can be individually
assigned to events and scheduled accordingly. The upper queues have historically been
managed as though they were a monolithic resource, where the resource is the entire
group of queues and each queue is a sub-instance. Because the status for these upper
queues was not directly connected to events, and the status flags are flattened in the
status register, a software polling approach was used to determine which of the queues
required attention. For this version of the AQM, this division between the upper and
lower queues has been somewhat formalized. This definition has the upper queues
providing all status, but in a flat fashion across each type of status register and the
addition of the ability to schedule the upper queues as if they were a monolithic
resource via a programmable event funnel into event bus flags. What these differences
mean will be discussed in later sections.
27.2 Feature List
• Provides queue functionality for NPEs and the Intel XScale
• Manages 64 independent queues
• Implements queues as FIFOs with circular buffer rotation in SRAM
• Implements read/write pointers for each queue in SRAM
• Programmable queue entry size supported (queues may be configured for 1, 2, or 4
word entries)
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
926
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IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager
(AQM)
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Processor
August 2006
Reference Number: 306262-004US