Interaction Of The Mmu, Instruction Cache, And Data Cache; Data Cache And Buffer Behavior When X = 1; Memory Operations That Impose A Fence - Intel IXP45X Developer's Manual

Intel
Table 6.

Data Cache and Buffer Behavior When X = 1

C B Cacheable
0 0
0 1
(Mini Data
1 0
1 1
Notes:
1. Normally, bufferable writes can coalesce with previously buffered data in the same address range.
2. See
register.
3.1.1.2.4 Memory Operation Ordering
A fence memory operation (memop) is one that guarantees all memops issued prior to
the fence will execute before any memop issued after the fence. Thus software may
issue a fence to impose a partial ordering on memory accesses.
Table 7 on page 72
Any swap (SWP or SWPB) to a page that would create a fence on a load or store is a
fence.
Table 7.

Memory Operations that Impose a Fence

Operation
load or store
3.1.1.2.5 Exceptions
The MMU may generate prefetch aborts for instruction accesses and data aborts for
data memory accesses. The types and priorities of these exceptions are described in
"Event Architecture" on page
Data address alignment checking is enabled by setting bit 1 of the Control Register
(CP15, register 1). Alignment faults are still reported even if the MMU is disabled. All
other MMU exceptions are disabled when the MMU is disabled.
3.1.2

Interaction of the MMU, Instruction Cache, and Data Cache

The MMU, instruction cache, and data/mini-data cache may be enabled/disabled
independently. The instruction cache can be enabled with the MMU enabled or disabled.
However, the data cache can only be enabled when the MMU is enabled. Therefore only
three of the four combinations of the MMU and data/mini-data cache enables are valid.
The invalid combination will cause undefined results.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
72
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
Bufferable Write Policy
- -
N Y
-
Cache)
Y Y
"Register 1: Control and Auxiliary Control Registers" on page 100
shows the circumstances in which memops act as fences.
X
load -
store 1
0
177.
Line
Allocation
Policy
- -
- -
- -
Read/Write
Write Back
Allocate
C
0
0
0
®
Notes
Unpredictable -- do not use
Writes will not coalesce into buffers
Cache policy is determined by MD field
2
of Auxiliary Control register
for a description of this
B
-
1
0
August 2006
Order Number: 306262-004US
Processor
1