Chip Select Address Allocation When There Are No 32-Mbyte Devices Programmed; Expansion Bus Memory Sizing - Intel IXP45X Developer's Manual

Figure 124. Chip Select Address Allocation when there are no 32-MByte Devices
Programmed
128
MBytes
cs_n[0] (alias)
cs_n[7]
cs_n[6]
cs_n[5]
128 cs_n[4]
MBytes
cs_n[3]
cs_n[2]
cs_n[1]
cs_n[0]
16 MB
The right side of
and Control (EXP_TIMING_CS) Register. A Timing and Control (EXP_TIMING_CS)
Register is implemented for each of the eight chip selects. Each chip select defines a
base region size of 512 bytes with the actual size of the region given by the formula
shown in
Expansion bus controller responds with an error response.
Figure 125. Expansion Bus Memory Sizing
Region Size = 2
For Examples of how to use this feature:
If bits 13:9 of Timing and Control (EXP_TIMING_CS0) Register 0 = "00000" an
address space of 2
If bits 13:9 of Timing and Control (EXP_TIMING_CS1) Register 1 = "10000" an
address space of 2
If bits 13:9 of Timing and Control (EXP_TIMING_CS2) Register 2 = "11110" an
address space of 2
If bits 13:9 of Timing and Control (EXP_TIMING_CS7) Register 7 = "00001" an
address space of 2
If there is a 32-MByte device programmed in any of the eight EXP_CS_TIMING
registers, a different memory map is used as shown in
the AHB address are translated to the lower 25 bits of the Expansion Bus address,
EX_ADDR [24:0]. Bits 27:25 of the AHB are used to decode one of eight chip-select
regions implemented by the Expansion bus, each region being 32 Mbyte. If a design
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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Intel IXP45X and Intel
base + 0xFFFFFFF
. .
.
base + 0x8000000
base + 0x7000000
base + 0x6000000
base + 0x5000000
base + 0x4000000
base + 0x3000000
base + 0x2000000
base + 0x1000000
base + 0x0000000
Figure 124 shows the implementation of bit 13:10 of the each Timing
Figure 125. If the AHB address is outside of the programmed region, the
(9+CNFG[4:1] + 16*CNFG[0])
9
= 512 Bytes is defined for chip select 0 EX_CS_N[0].
17
= 128KBytes is defined for chip select 1 EX_CS_N[1].
24
= 16Mbytes is defined for chip select 2 EX_CS_N[2].
25
= 32Mbytes is defined for chip select 7 EX_CS_N[7].
®
IXP46X Product Line of Network Processors—Expansion Bus
cs_n[x]
Figure
Controller
CNFG[4:1] = 0b1111
SIZE = 16 MBytes
0b1110 : 8 MBytes
0b1101 : 4 MBytes
0b1100 : 2 MBytes
0b1011 : 1 MBytes
0b0000 : 512 Bytes
B4398-01
126. The lower 25 bits of
August 2006
Order Number: 306262-004US