Interrupt Controller Memory Mapped Registers; Register Legend; Error Enable Register; Interrupt Controller Register Descriptions - Intel IXP45X Developer's Manual

Interrupt Controller—Intel
For example, interrupt number 1 (Ethernet NPE B) is the highest-priority IRQ interrupt,
the value obtained when reading the IRQ Highest-Priority Interrupt Register would be
hexadecimal 0x00000008. A value of 0 — returned when reading the IRQ Highest-
Priority Register — signifies that no IRQ interrupts are pending.
The IRQ Highest-Priority Register will be reset to a value of 0. The FIQ Highest-Priority
Register will behave in an identical fashion to the IRQ Highest-Priority Register.
17.5

Error Enable Register

The ERROR_EN2 register is what defines the difference between the two so-called
classes of interrupts. Interrupts [31:0] are by definition (for compatibility reasons)
never of the error class. Only the new interrupts [63:32] can be in this class. The
purpose of the error class of interrupts is to force the servicing of error conditions
above normal conditions because they usually represent some kind of failure condition.
For example, NPE A may have parity bits added to its data memory. If a parity error is
detected an interrupt is generated. However if that interrupt's error enable bit is TRUE,
the parity error takes unconditional priority over the "normal" positional priority
interrupts. Note that this does not alter the value of the number reported in the
encoding status registers, only that the priority scheme is altered.
The bit in ERROR_EN2[0] corresponds to interrupt 32 and the bit in ERROR_EN2[31]
corresponds to interrupt 63. If the interrupt is enabled, the error enable is TRUE, and
the interrupt becomes active, that interrupt takes priority over all other interrupts. If
more than one error class of interrupts is being reported, the highest positional priority
is reported in the encoding status register assigned to that interrupt (i.e. FIQ or IRQ).
17.6

Interrupt Controller Register Descriptions

Table 262.

Register Legend

Attribute
RV
PR
RS
RW
RW1C
Table 263. Interrupt Controller Memory Mapped Registers (Sheet 1 of 2)
Address
0xC8003000
0xC8003004
0xC8003008
0xC8003020
0xC8003024
0xC8003028
0xC800302C
0xC8003030
0xC8003034
August 2006
Reference Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Legend
Reserved
Preserved
Read/Set
Read/Write
Normal Read
Write '1' to clear
Access
RO
RW
RW
RO
RW
RW
RO
RO
RW
Attribute Legend
RC Read Clear
RO Read Only
WO Write Only
NA Not Accessible
Normal Read
RW1S
Write '1' to set
Name
INTR_ST Interrupt Status Register
INTR_EN Interrupt Enable Register
INTR_SEL Interrupt Select Register
Interrupt Status Register 2
INTR_ST2
INTR_EN2 Interrupt Enable Register 2
INTR_SEL2 Interrupt Select Register 2
INTR_IRQ_ST2 IRQ Status register 2
INTR_FIQ_ST2 FIQ status Register 2
ERROR_EN2 Error Priority Enable Register
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Description
Developer's Manual
811