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HSS Coprocessor—Intel
IXP45X and Intel
the error register, all FIFO errors and the FIFOs themselves in the HSS core for that
direction are cleared. When the NPE Core reads the error register, the RX condition
signals are cleared.
The HSS can indicate TX and RX errors in the same HSS core or different HSS core
simultaneously. Meaning that the HSS can indicate an HSS core 0 RX and HSS core 1
TX error simultaneously. During under/overflow the tx data pin is set to the
programmed unassigned value.
Unexpected frame pulse error is defined as a frame pulse that occurs where one should
not exist (incorrect frame length, frame pulse offset incorrectly programmed, and so
on). If this happens simultaneously with an over/underflow error, the unexpected frame
pulse is given priority.
After the NPE Core reads the error register, the FIFOs in that direction and the condition
flags to the NPE Core are cleared.
A frame pulse not present where one is expected is not considered as an error and
normal operations are maintained.
Note:
Error conditions are not signaled to the NPE Core while that core is not synchronized to
the frame pulse.
13.3.5
56K Mode
Certain protocols require "bit stealing", meaning certain bits are dropped (do not carry
information). In E1 mode for example, the HSS transports at 2.048Kbps which gives
64K per channel (32 channels). 56K mode places a value (default = 0) in the MSb of
each timeslot transmitted (depending on the endianness it can be at the left or right
side of the byte).
As this value in the MSb does not carry information about any of the channels, it
therefore reduces the capacity per channel to 56 Kbps,
(8000 frames * 32 timeslots per frame * 7 bits per timeslot / 32 channels = 56 Kbyte
per channel).
The value placed by the HSS into the MSb is programmable by the NPE Core. The HSS
performs this by overriding FIFO control for that bit in that timeslot, thus preventing
FIFO data from been accessed.
The 56K mode has no effect on RX data, except that it is presumed that the transmitter
at the far end of the line has performed 56K operations on the stream. Received
"stolen" bits are placed in the RX FIFO and are treated as data by the HSS.
13.3.6
Frameless Data Protocol Support
The HSS doesn't need to have a frame pulse supplied in order to transmit/receive data.
In this case, the HSS should have its lookup tables/frame lengths/programmed as if it
was using the 512-KHz GCI protocol. The HSS immediately assumes synchronization
and uses internal logic that predicts frame pulses (for gapped frame pulses) to
coordinate transmission and reception of data. The internal frame generator is not used
nor is it sent out on the frame pin (for either TX/RX).
13.3.7
Loopback
Loopback is a debug function that can be used to deduce and debug problems observed
with the system.
August 2006
Reference Number: 306262-004US
®
IXP46X Product Line of Network Processors
®
Intel
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Developer's Manual
733
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