Table of Contents
Advertisement
USB 2.0 Host Controller—Intel
pointer is the page 1 pointer and Current Offset has rolled to one, and both are written
back to the overlay area. The transactions continue for the rest of the buffer, with the
host controller automatically moving to the next page pointer (i.e. C_Page) when
necessary. There are three conditions for how the host controller handles C_Page.
• The current transaction does not span a page boundary. The value of C_Page is not
adjusted by the host controller.
• The current transaction does span a page boundary. The host controller must
detect the page cross condition and advance to the next buffer while streaming
data to/from the USB.
• The current transaction completes on a page boundary (i.e. the last byte moved for
the current transaction is the last byte in the page for the current page pointer).
The host controller must increment C_Page before writing back status for the
transaction.
Note that the only valid adjustment the host controller may make to C_Page is to
increment by one.
9.14.10.7
Adding Interrupt Queue Heads to the Periodic Schedule
The link path(s) from the periodic frame list to a queue head establishes in which
frames a transaction can be executed for the queue head. Queue heads are linked into
the periodic schedule so they are polled at the appropriate rate. System software sets a
bit in a queue head's S-Mask to indicate which micro-frame with-in a 1-ms period a
transaction should be executed for the queue head. Software must ensure that all
queue heads in the periodic schedule have S-Mask set to a non-zero value. An S-mask
with a zero value in the context of the periodic schedule yields undefined results.
If the desired poll rate is greater than one frame, system software can use a
combination of queue head linking and S-Mask values to spread interrupts of equal poll
rates through the schedule so that the periodic bandwidth is allocated and managed in
the most efficient manner possible. Some examples are illustrated in
Table 177.
Example Periodic Reference Patterns for Interrupt Transfers with 2-ms Poll
Rate
Frame #
Reference
Sequence
0, 2, 4, 6, 8, etc.
S-Mask = 01h
0, 2, 4, 6, 8, etc.
S-Mask = 02h
9.14.10.8
Managing Transfer Complete Interrupts from Queue Heads
The host controller will set an interrupt to be signaled at the next interrupt threshold
when the completed transfer (qTD) has an Interrupt on Complete (IOC) bit set to a
one, or whenever a transfer (qTD) completes with a short packet. If system software
needs multiple qTDs to complete a client request (i.e. like a control transfer) the
intermediate qTDs do not require interrupts. System software may only need a single
interrupt to notify it that the complete buffer has been transferred. System software
may set IOC's to occur more frequently. A motivation for this may be that it wants early
notification so that interface data structures can be re-used in a timely manner.
August 2006
Order Number: 306262--, Revision: 004US
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
A queue head for the bInterval of 2 ms (16 micro-frames) is linked into the periodic
schedule so that it is reachable from the periodic frame list locations indicated in the
previous column. In addition, the S-Mask field in the queue head is set to 01h, indicating
that the transaction for the endpoint should be executed on the bus during micro-frame 0
of the frame.
Another example of a queue head with a bInterval of 2 milliseconds is linked into the
periodic frame list at exactly the same interval as the previous example. However, the S-
Mask is set to 02h indicating that the transaction for the endpoint should be executed on
the bus during micro-frame 1 of the frame.
Intel
Description
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors
Table
177.
Developer's Manual
451
Advertisement
Table of Contents
