Multiply Instruction Timings - Intel IXP45X Developer's Manual

®
Intel XScale Processor—Intel
Table 83. Data Processing Instruction Timings (Sheet 2 of 2)
Mnemonic
CMN
CMP
EOR
MOV
MVN
ORR
RSB
RSC
SBC
SUB
TEQ
TST
† If the next instruction needs to use the result of the data processing for a shift by immediate or as Rn
in a QDADD or QDSUB, one extra cycle of result latency is added to the number listed.
3.9.4.4

Multiply Instruction Timings

Table 84. Multiply Instruction Timings (Sheet 1 of 2)
Mnemonic
MLA
MUL
† If the next instruction needs to use the result of the multiply for a shift by immediate or as Rn in a
QDADD or QDSUB, one extra cycle of result latency is added to the number listed.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
<shifter operand> is NOT a Shift/
Rotate by Register
Minimum Issue
Latency
1
1
1
1
1
1
1
1
1
1
1
1
Rs Value S-Bit
(Early Valu
Termination) e
Rs[31:15] = 0
0x00000
or
1
Rs[31:15] = 0x1FFFF
Rs[31:27] = 0x00 0
or
1
Rs[31:27] = 0x1F
0
all others
1
Rs[31:15] = 0
0x00000
or
1
Rs[31:15] = 0x1FFFF
Rs[31:27] = 0x00 0
or
1
Rs[31:27] = 0x1F
0
all others
1
Intel
<shifter operand> is a Shift/Rotate
<shifter operand> is RRX
Minimum Result Minimum Issue
†
Latency Latency
1
1
1
1
1
1
1
1
1
1
1
1
Minimum
Minimum Result
Issue
Latency
Latency
1 2
2 2
1 3
3 3
1 4
4 4
1 2
2 2
1 3
3 3
1 4
4 4
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
by Register OR
Minimum Result
†
Latency
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
2 2
Minimum Resource
†
Latency (Throughput)
1
2
2
3
3
4
1
2
2
3
3
4
Developer's Manual
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