Multiple Performance Monitoring Run Statistics; Examples - Intel IXP45X Developer's Manual

Intel
PMN1 counts the number of data TLB table-walks, which occurs when there is a TLB
miss. If the data TLB is disabled PMN1 will not increment.
The statistic derived from these two events is:
Data TLB miss-rate. This is derived by dividing PMN1 by PMN0.
3.7.5

Multiple Performance Monitoring Run Statistics

There may be times when more than four events need to be monitored for performance
tuning. In this case, multiple performance monitoring runs can be done, capturing
different events from each run. For example, the first run could monitor the events
associated with instruction cache performance and the second run could monitor the
events associated with data cache performance. By combining the results, statistics like
total number of memory requests could be derived.
3.7.6

Examples

In this example, the events selected with the Instruction Cache Efficiency mode are
monitored and CCNT is used to measure total execution time. Sampling time ends
when PMN0 overflows which will generate an IRQ interrupt.
Example 14. Configuring the Performance Monitor
; Configure the performance monitor with the following values:
; EVTSEL.evtCount0 = 7, EVTSEL.evtCount1 = 0 instruction cache efficiency
; INTEN.inten = 0x7 set all counters to trigger an interrupt on overflow
; PMNC.C = 1 reset CCNT register
; PMNC.P = 1 reset PMN0 and PMN1 registers
; PMNC.E = 1 enable counting
MOV R0,#0x700
MCR P14,0,R0,C8,c1,0
MOV R0,#0x7
MCR P14,0,R0,C4,c1,0
MCR P14,0,R0,C0,c1,0
; Counting begins
Counter overflow can be dealt with in the IRQ interrupt service routine as shown below:
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
166
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IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
; setup EVTSEL
; setup INTEN
; setup PMNC, reset counters & enable
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Processor
August 2006
Order Number: 306262-004US