Sourceuuid0_Low Register (Per Channel) - Intel IXP45X Developer's Manual

Intel
19.5.2.22

SourceUUID0_Low Register (Per Channel)

Register Name:
Block
RegBlockAddress
Base Address:
Source UUID0 Low Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
When a Delay_Req message in Master mode, or a Sync message in Slave
mode, is received, the Source UUID of the message is captured. The source
SourceUUID0 UUID is located in bytes 64 through 69 of the Ethernet message, and this
31:0
_Low register contains the lower 32 bits of the source UUID. This register is read-
only. At reset, the value in the register is 0, which is not a valid Source UUID
value.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
854
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IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization
Offset Address
SourceUUID0_Low[31:0]
*Address offsets per channel...
Channel 0 = 0x058
Channel 1 = 0x078
Channel 2 = 0x098
Description
TS_SrcUUID0Lo
0x058*
Reset Value
8
TS_SrcUUID0Lo
Hardware Assist (TSYNC)
0x0
Access: (See below.)
7 6 5 4 3 2 1
Reset
Access
Value
0 RO
August 2006
Order Number: 306262-004US
0