Intel IXP45X Developer's Manual page 10

8.5.8 UDC Endpoint 6 Control/Status Register................................................... 307
8.5.8.1
8.5.8.2
8.5.8.3
8.5.8.4
8.5.8.5
8.5.8.6
8.5.8.7
8.5.8.8
8.5.9 UDC Endpoint 7 Control/Status Register................................................... 309
8.5.9.1
8.5.9.2
8.5.9.3
8.5.9.4
8.5.9.5
8.5.9.6
8.5.9.7
8.5.9.8
8.5.10 UDC Endpoint 8 Control/Status Register................................................... 311
8.5.10.1 Transmit FIFO Service (TFS) ..................................................... 311
8.5.10.2 Transmit Packet Complete (TPC) ............................................... 311
8.5.10.3 Flush Tx FIFO (FTF) ................................................................. 312
8.5.10.4 Transmit Underrun (TUR) ......................................................... 312
8.5.10.5 Bit 4 Reserved ........................................................................ 312
8.5.10.6 Bit 5 Reserved ........................................................................ 312
8.5.10.7 Bit 6 Reserved ........................................................................ 312
8.5.10.8 Transmit Short Packet (TSP) ..................................................... 312
8.5.11 UDC Endpoint 9 Control/Status Register................................................... 313
8.5.11.1 Receive FIFO Service (RFS) ...................................................... 313
8.5.11.2 Receive Packet Complete (RPC)................................................. 313
8.5.11.3 Receive Overflow (ROF) ........................................................... 313
8.5.11.4 Bit 3 Reserved ........................................................................ 313
8.5.11.5 Bit 4 Reserved ........................................................................ 314
8.5.11.6 Bit 5 Reserved ........................................................................ 314
8.5.11.7 Receive FIFO Not Empty (RNE).................................................. 314
8.5.11.8 Receive Short Packet (RSP) ...................................................... 314
8.5.12 UDC Endpoint 10 Control/Status Register................................................. 315
8.5.12.1 Transmit FIFO Service (TFS) ..................................................... 315
8.5.12.2 Transmit Packet Complete (TPC) ............................................... 315
8.5.12.3 Flush Tx FIFO (FTF) ................................................................. 315
8.5.12.4 Transmit Underrun (TUR) ......................................................... 315
8.5.12.5 Sent STALL (SST).................................................................... 316
8.5.12.6 Force STALL (FST)................................................................... 316
8.5.12.7 Bit 6 Reserved ........................................................................ 316
8.5.12.8 Transmit Short Packet (TSP) ..................................................... 316
8.5.13 UDC Endpoint 11 Control/Status Register................................................. 317
8.5.13.1 Transmit FIFO Service (TFS) ..................................................... 317
8.5.13.2 Transmit Packet Complete (TPC) ............................................... 317
8.5.13.3 Flush Tx FIFO (FTF) ................................................................. 318
8.5.13.4 Transmit Underrun (TUR) ......................................................... 318
8.5.13.5 Sent STALL (SST).................................................................... 318
8.5.13.6 Force STALL (FST)................................................................... 318
8.5.13.7 Bit 6 Reserved ........................................................................ 318
8.5.13.8 Transmit Short Packet (TSP) ..................................................... 318
8.5.14 UDC Endpoint 12 Control/Status Register................................................. 319
8.5.14.1 Receive FIFO Service (RFS) ...................................................... 319
8.5.14.2 Receive Packet Complete (RPC)................................................. 320
8.5.14.3 Bit 2 Reserved ........................................................................ 320
8.5.14.4 Bit 3 Reserved ........................................................................ 320
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
10
® ®
Intel IXP45X and Intel
Transmit FIFO Service (TFS) ..................................................... 307
Transmit Packet Complete (TPC) ............................................... 307
Flush Tx FIFO (FTF) ................................................................. 307
Transmit Underrun (TUR) ......................................................... 307
Sent STALL (SST).................................................................... 307
Force STALL (FST)................................................................... 308
Bit 6 Reserved ........................................................................ 308
Transmit Short Packet (TSP) ..................................................... 308
Receive FIFO Service (RFS) ...................................................... 309
Receive Packet Complete (RPC)................................................. 309
Bit 2 Reserved ........................................................................ 309
Bit 3 Reserved ........................................................................ 309
Sent Stall (SST) ...................................................................... 309
Force Stall (FST) ..................................................................... 310
Receive FIFO Not Empty (RNE).................................................. 310
Receive Short Packet (RSP) ...................................................... 310
IXP46X Product Line of Network Processors—Contents
August 2006
Order Number: 306262-004US