Periodic Schedule Frame Boundaries Versus Bus Frame Boundaries; Frame Boundary Relationship Between Hs Bus And Fs/Ls Bus - Intel IXP45X Developer's Manual

USB 2.0 Host Controller—Intel
9.14.5 Periodic Schedule Frame Boundaries versus Bus Frame
Boundaries
The USB Specification Revision 2.0 requires that the frame boundaries (SOF frame
number changes) of the high-speed bus and the full- and low-speed bus(s) below USB
2.0 hubs be strictly aligned. Super-imposed on this requirement is that USB 2.0 hubs
manage full- and low-speed transactions via a micro-frame pipeline (see start- (SS)
and complete- (CS) splits illustrated in
between HS bus and FS/LS Bus" on page
boundary model into the host controller interface schedule architecture creates tension
(complexity for both hardware and software) between the frame boundaries and the
scheduling mechanisms required to service the full- and low-speed transaction
translator periodic pipelines.
Figure 57.

Frame Boundary Relationship between HS bus and FS/LS Bus

Frame Boundary
HS Bus
FS/LS Bus
The simple projection, as
and FS/LS Bus" on page 423
scheduling on both the beginning and end of a frame. In order to reduce the complexity
for hardware and software, the host controller is required to implement a one micro-
frame phase shift for its view of frame boundaries. The phase shift eliminates the
beginning of frame and frame-wrap scheduling boundary conditions.
The implementation of this phase shift requires that the host controller use one register
value for accessing the periodic frame list and another value for the frame number
value included in the SOF token. These two values are separate, but tightly coupled.
The periodic frame list is accessed via the Frame List Index Register (FRINDEX)
documented in
Section 9.14.4, "Schedule Traversal Rules" on page
the micro-frame number. The SOF value is coupled to the value of FRINDEX[13:3].
Both FRINDEX[13:3] and the SOF value are incremented based on FRINDEX[2:0]. It is
required that the SOF value be delayed from the FRINDEX value by one micro-frame.
The one micro-frame delay yields host controller periodic schedule and bus frame
boundary relationship as illustrated in
Frame Boundaries to Bus Frame Boundaries" on page
software to trivially schedule the periodic start and complete-split transactions for full-
and low-speed periodic endpoints, using the natural alignment of the periodic schedule
interface. The reasons for selecting this phase-shift are beyond the scope of this
specification.
Figure 58, "Relationship of Periodic Schedule Frame Boundaries to Bus Frame
Boundaries" on page 424
schedule frame boundaries and bus frame boundaries. To aid the presentation, two
terms are defined. The host controller's view of the 1-millisecond boundaries is called
H-Frames. The high-speed bus's view of the 1-ms boundaries is called B-Frames.
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
7 0 1
SS CS
Figure 57, "Frame Boundary Relationship between HS bus
illustrates, introduces frame-boundary wrap conditions for
Section 9.12.4, "FRINDEX" on page 378
illustrates how periodic schedule data structures relate to
Intel
Figure 57, "Frame Boundary Relationship
423). A simple, direct projection of the frame
Micro-frame numbers(s)
2 3 4 5
CS CS SS CS CS
and initially illustrated in
418. Bits FRINDEX[2:0], represent
Figure 58, "Relationship of Periodic Schedule
424. This adjustment allows
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
6 7 0
CS CS CS
B4500-01
Developer's Manual
423